Polysilicon Mesh Diodes for ESD Protection in CMOS I/O
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Solution Overview
Problem
Current ESD protection mechanisms in integrated circuits face challenges with high voltage clamping, high current limitation, and heat dissipation, particularly in nanometer devices where gate oxides are vulnerable, and high-speed circuits require small input capacitance and effective ESD protection, which is often achieved at the cost of large silicon area and high input capacitance.
Innovation Solution
The implementation of a mesh structure of diodes constructed from polysilicon or active region bodies, which are fabricated using standard CMOS logic processes, allowing for high ESD immunity, low input capacitance, small I/O size, and low cost, with diodes having a turn-on voltage of about 0.6V and adjustable breakdown voltage, enabling effective clamping and heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional junction diodes are used for ESD protection, then high voltage clamping and high current limitation are achieved, but large silicon area and high input capacitance are required
Solution Approach 1:
The invention segments the ESD protection function into multiple small diode structures arranged in a mesh pattern, where each diode is formed by intersecting polysilicon lines. This segmentation allows the ESD protection capability to be distributed across the entire I/O pad area, achieving effective protection without requiring large dedicated silicon area for separate protection devices.
Solution Approach 2:
The polysilicon mesh structure serves multiple functions simultaneously: it provides ESD protection through diode action, maintains low input capacitance due to its distributed nature, and achieves low breakdown voltage through the intrinsic properties of the polysilicon-junction. This multi-functionality eliminates the need for separate dedicated ESD protection structures that would consume additional silicon area.
2Reliability
If conventional junction diodes are used for ESD protection, then high voltage clamping is achieved, but high input capacitance is incurred
Solution Approach 1:
By segmenting the ESD protection into many small distributed diodes across the mesh structure, the total input capacitance is divided into numerous small capacitive elements. The distributed capacitance of individual small diodes is significantly lower than that of a single large diode, thereby achieving low input capacitance while maintaining effective ESD protection capability.
3Ease of manufacture
If standard CMOS processes are used for fabrication, then low cost and ease of manufacture are achieved, but additional masks or process steps are typically required
Solution Approach 1:
The polysilicon mesh structure is formed using standard polysilicon deposition and patterning processes already present in CMOS fabrication. The same polysilicon layers used for transistor gates and interconnects are utilized to create the ESD protection diodes, making the process universal and eliminating the need for additional dedicated ESD protection fabrication steps.
Solution Approach 2:
The invention merges the ESD protection structure formation with the existing polysilicon processing steps in CMOS fabrication. By combining the ESD diode pattern formation with standard polysilicon gate or interconnect formation steps, the process integrates seamlessly without requiring separate masks or additional process steps, thereby reducing fabrication complexity and cost.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution provides high-performance ESD protection with reduced input capacitance and smaller area requirements, effectively clamping high voltages and dissipating heat, while maintaining low costs and compatibility with standard CMOS processes.
Implementation Method 1
the junction diodes 12 and 11 have a turn-on voltage of about 0.7V and a breakdown voltage of about 5V
Implementation Method 2
When a high positive voltage is applied to the I/O pad 13, the I/O pad 13 can be clamped to VDD+0.7 if the diode 11 is turned on
Implementation Method 3
the high heat generated by the high current during diode turn-on or breakdown can be quickly dissipated by guard rings surrounding the P terminal or N terminal of the diodes
Data Source
AI summary
A bipolar junction transistor built with a mesh structure of cells provided on a semiconductor body is disclosed. The mesh structure has at least one emitter cell with a first type of implant. At least one emitter cell has at least one side coupled to at least one cell with a first type of implant to serve as collector of the bipolar. The spaces between the emitter and collector cells are the intrinsic base of a bipolar device. At least one emitter cell has at least one vortex coupled to at least one cell with a second type of implant to serve as the extrinsic base of the bipolar. The emitter, collector, or base cells can be arbitrary polygons as long as the overall geometry construction can be very compact and expandable. The implant regions between cells can be separated with a space. A silicide block layer can cover the space and overlap into at least a portion of both implant regions.