Polysilicon Pillar BJT with Self-Aligned Memory Element
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Solution Overview
Problem
Phase change memory cells with field effect transistor access devices face challenges in achieving necessary current for phase change due to low current drive, and integrating bipolar junction transistors with CMOS peripheral circuitry is complex and difficult, especially in high-density memory devices with tight manufacturing tolerances.
Innovation Solution
Memory cells with self-aligned bipolar junction transistor access devices using a doped polysilicon emitter and an insulating element, where the memory element is formed within an opening defined by the insulating element, reducing current requirements through concentrated current density and thermal isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If field effect transistors are used as access devices, then device complexity is reduced and CMOS integration is easier, but current drive capability is insufficient to achieve necessary current for phase change
Solution Approach 1:
The patent merges the advantages of bipolar junction transistors (high current drive) with CMOS compatibility by using a simplified BJT structure that can be integrated with standard CMOS peripheral circuitry. The self-aligned fabrication process combines multiple functions into a unified manufacturing flow that achieves both high current capability and manufacturing simplicity.
Solution Approach 2:
The patent changes the transistor type from field effect to bipolar junction, fundamentally altering the electrical characteristics to achieve higher current drive capability while maintaining compatibility with CMOS integration through careful design of the BJT structure and fabrication process.
2Power
If bipolar junction transistors are used as access devices, then current drive capability is improved, but device complexity and manufacturing integration with CMOS peripheral circuitry becomes difficult
Solution Approach 1:
The patent changes the transistor type from field effect to bipolar junction, fundamentally altering the electrical characteristics to achieve higher current drive capability while maintaining compatibility with CMOS integration through careful design of the BJT structure and fabrication process.
Solution Approach 2:
The self-aligned fabrication process uses the sacrificial element as a template or copy of the desired final structure, allowing the memory element to be precisely positioned without requiring complex alignment steps, thereby simplifying the manufacturing process.
3Power
If phase change memory element size is reduced to achieve higher current density, then current magnitude is reduced, but manufacturing precision requirements become extremely tight
Solution Approach 1:
The self-aligned fabrication process uses the sacrificial element as a template or copy of the desired final structure, allowing the memory element to be precisely positioned without requiring complex alignment steps, thereby simplifying the manufacturing process.
Solution Approach 2:
The sacrificial element serves multiple functions: it defines the location and dimensions of the memory element, provides structural support during fabrication, and is automatically removed to create the final structure. This self-service approach eliminates the need for separate alignment and positioning steps.
4Manufacturing precision
If sacrificial element is removed to form via, then memory element location is precisely defined, but additional manufacturing steps are added
Solution Approach 1:
The patent merges the sacrificial element removal step with the via formation step, and combines the memory element deposition with the insulating element formation, reducing the total number of separate manufacturing cycles while maintaining precise alignment.
Solution Approach 2:
The sacrificial element is formed in advance during the standard CMOS fabrication process, before the memory element is deposited. This preliminary action ensures that the memory element location is pre-defined and aligned with other circuit features, eliminating the need for subsequent alignment operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution allows for phase change memory cells with bipolar junction transistor access devices that are compatible with CMOS peripheral circuitry, reducing current needs and addressing manufacturing complexity and tolerance issues, thereby enhancing the performance and density of high-density memory devices.
Implementation Method 1
The small width concentrates current density within the memory element, thereby reducing the magnitude of the current needed to induce a phase change in the active region
Implementation Method 2
the insulating element may provide some thermal isolation to the active region, which also helps to reduce the amount of current necessary to induce a phase change
Implementation Method 3
The change from the amorphous to the crystalline state is generally a lower current operation. The change from crystalline to amorphous, referred to as reset herein, is generally a higher current operation, which includes a short high current density pulse to melt or breakdown the crystalline structure
Implementation Method 4
Phase change based memory materials, like chalcogenide based materials and similar materials, can be caused to change phase between an amorphous state and a crystalline state by application of electrical current
Data Source
AI summary
Memory cells having memory elements self-aligned with the emitters of bipolar junction transistor access devices are described herein, as well as methods for manufacturing such devices. A memory device as described herein comprises a plurality of memory cells. Memory cells in the plurality of memory cells include a bipolar junction transistor comprising an emitter comprising a pillar of doped polysilicon. The memory cells include an insulating element over the emitter and having an opening extending through the insulating layer, the opening centered over the emitter. The memory cells also include a memory element within the opening and electrically coupled to the emitter.