Polysilicon Plug Oxidation for Memory Device Manufacturing
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Solution Overview
Problem
In the manufacturing of memory devices, particularly in 0.11-um CMOS processing, the miniaturization of bit line contact holes leads to increased risk of electric shorts due to residual polysilicon layers causing poly stringers, which conventional methods attempt to address through over CMP, but this results in unintended thinning of cap nitride layers and potential word-line to bit-line shorts.
Innovation Solution
A method involving the formation of gate structures with a cap layer, followed by a polysilicon layer filling the gaps, a planarization process to create polysilicon plugs, and an oxidation process to convert residual polysilicon layers to silicon oxide, preventing poly stringers and ensuring the cap nitride layer's integrity, thus avoiding shorts during the formation of conductive layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If chemical mechanical polishing (CMP) is used to remove residual polysilicon layer, then poly stringer is avoided, but cap nitride layer is thinned and gate conductor is exposed
Solution Approach 1:
The patent extracts the harmful residual polysilicon layer from the gate structure surface through selective removal processes, while preserving the cap nitride layer. This is achieved by using etch-selective materials and processes that remove only the polysilicon without affecting the cap nitride layer thickness
Solution Approach 2:
The patent applies different removal mechanisms to different locations: mechanical polishing for bulk polysilicon removal and selective etching for residual polysilicon removal. This localized approach ensures complete polysilicon removal from critical areas while preserving the cap nitride layer in other areas
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively prevents bit-line to bit-line shorts by converting residual polysilicon layers to silicon oxide, maintaining the cap nitride layer's thickness and preventing electrical shorts, while allowing for proper connection of conductive layers without exposing the gate conductor.
Implementation Method 1
performing an oxidation process after the planarization process, converting a part of the polysilicon plug and a residual polysilicon layer over the gate structure to silicon oxide
Data Source
AI summary
The disclosure provides a method for manufacturing a memory device, including: providing a plurality of gate structures formed on a substrate, wherein the gate structures comprise a cap layer disposed on the top of the gate structure, and each two adjacent gate structures are separated by a gap; blanketly forming a polysilicon layer on the substrate to fill the gap; performing a planarization process to the polysilicon layer, obtaining a polysilicon plug; and performing an oxidation process after the planarization process, converting a part of the polysilicon plug and a residual polysilicon layer over the gate structure to silicon oxide.