Polysilicon Resistance Elements via Stress Modulation
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Solution Overview
Problem
The existing methods for forming resistance elements in semiconductor devices require separate masks and doping conditions for each resistance value, leading to increased costs due to the need for different impurity amounts in polysilicon layers.
Innovation Solution
A semiconductor device and fabrication method where multiple resistance elements are formed using polysilicon layers with matching impurity amounts, achieving different resistance values by using interlayer insulation films and metal layers to apply stress, thereby adjusting the resistance values without the need for multiple doping masks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If separate masks and doping conditions are used for each resistance value, then different resistance values can be achieved, but manufacturing costs increase
Solution Approach 1:
The patent applies parameter changes by modifying the physical state and configuration of the polysilicon layer rather than changing impurity amounts. Specifically, it controls resistance values by adjusting layer thickness, stacking configuration, and crystalline orientation parameters, allowing multiple resistance values to be achieved from a single uniformly doped polysilicon layer, thereby eliminating the need for multiple masks and reducing manufacturing costs
Solution Approach 2:
The patent makes a single polysilicon layer serve multiple functions by creating different resistance elements with varying resistance values from the same layer. Through selective patterning and stacking configurations, one polysilicon layer with uniform impurity distribution can produce multiple resistance elements with different resistance values, replacing the need for multiple separately doped layers
2Manufacturing precision
If multiple masks are prepared for different resistance values, then different impurity amounts can be implanted, but the fabrication process becomes more complex
Solution Approach 1:
The patent extracts the variable parameter from the impurity amount and relocates it to geometric and structural parameters. By removing the need for variable doping concentrations, the fabrication process is simplified to use only a single mask for patterning, while resistance differentiation is achieved through extracted geometric variations in layer thickness and stacking arrangements
Solution Approach 2:
The patent inverts the conventional approach by not varying impurity amounts to achieve different resistance values. Instead, it maintains uniform impurity distribution and inverts the control mechanism to vary resistance through geometric configuration, layer stacking, and thickness parameters, thereby simplifying the doping process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the cost-effective production of semiconductor devices with multiple resistance elements having different resistance values, simplifying the fabrication process while maintaining precise control over resistance values.
Implementation Method 1
a first resistance element formed of a first polysilicon layer that contains impurities; a second resistance element provided on a same surface as the first polysilicon layer, and formed of a second polysilicon layer that contains an equal amount of impurities to the first polysilicon layer
Data Source
AI summary
A semiconductor device including: a first resistance element formed of a first polysilicon layer that contains impurities; a second resistance element provided on a same surface as the first polysilicon layer, and formed of a second polysilicon layer that contains an equal amount of impurities to the first polysilicon layer; a first interlayer insulation film provided so as to cover the first resistance element and the second resistance element; and a first metal layer provided on the first interlayer insulation film so as to cover the second resistance element with the first interlayer insulation film disposed therebetween.