Polycrystalline Silicon Resistor Resistance Adjustment
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Solution Overview
Problem
In integrated circuit fabrication, polysilicon resistors exhibit high resistance issues due to charge carrier depletion at the gate dielectric interface, leading to reduced effective capacitance and impedance matching problems in advanced transistor configurations, particularly in analog and RF applications.
Innovation Solution
The use of polycrystalline silicon in combination with titanium nitride-based conductive cap layers allows for efficient adjustment of resistance values without deteriorating the crystalline state, utilizing aluminum-containing titanium nitride to achieve resistance values approximately 20% higher than amorphous silicon/titanium nitride combinations, enabling precise impedance matching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If polysilicon material is used for resistors in advanced transistor configurations, then the resistor structures can be formed using standard CMOS processes, but charge carrier depletion at the gate dielectric interface causes high resistance and reduced effective capacitance
Solution Approach 1:
The patent changes the material parameter from standard polysilicon to heavily-doped polysilicon with specific doping concentrations (1E19 to 1E21 atoms/cm³). This parameter change increases carrier concentration and reduces depletion effects, thereby lowering resistance and improving effective capacitance while maintaining CMOS process compatibility
Solution Approach 2:
The patent creates a composite structure by combining heavily-doped polysilicon with specific dielectric materials (such as silicon nitride or silicon oxide) in a stacked configuration. This composite approach leverages the high carrier concentration of doped polysilicon and the electrical properties of the dielectric to achieve stable resistance and improved capacitance characteristics
2Manufacturing precision
If single crystalline silicon resistor is used to achieve higher resistance values, then impedance matching for analog and RF circuits is improved, but the resistance value cannot be precisely adjusted and parasitic capacitance increases
Solution Approach 1:
The patent applies local quality by creating laterally extended resistor structures with controlled dimensions and doping profiles. By varying the local doping concentration and geometric dimensions (width, length, thickness) of the polysilicon resistor regions, precise resistance values can be achieved without significantly increasing parasitic capacitance, enabling better impedance matching for analog and RF circuits
3Reliability
If polysilicon gate electrode material is replaced with high-k dielectric and metal combinations, then charge carrier depletion is reduced and conductivity is improved, but the manufacturing process complexity increases
Solution Approach 1:
The patent uses lightly-doped polysilicon as a temporary or sacrificial layer during fabrication that is later replaced or modified. This disposable polysilicon structure simplifies the overall process by avoiding the need for complex high-k dielectric and metal gate stack formation, while still achieving the desired electrical characteristics in the final device
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for precise resistance value adjustment and improved transistor performance by maintaining high conductivity and reducing leakage currents, addressing the limitations of previous polysilicon resistor designs in replacement gate processes.
Implementation Method 1
polysilicon may suffer from charge carrier depletion at the vicinity of the interface positioned between the gate dielectric material and the polysilicon material
Implementation Method 2
the resistance of the formed polysilicon resistors is too low... efficient adjustment of resistance values... achieve resistance values approximately 20% higher than amorphous silicon/titanium nitride combinations
Data Source
AI summary
Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, an integrated circuit includes a first transistor structure that includes an etch-stop material layer, a first workfunction material layer disposed over the etch-stop material layer, a second workfunction material layer disposed over the first workfunction material layer, and a metal fill material disposed over the second workfunction material layer. The integrated circuit further includes a second transistor structure that includes a layer of the etch-stop material, a layer of the second workfunction material disposed over the etch-stop material layer, and a layer of the metal fill material disposed over the second workfunction material layer. Still further, the integrated circuit includes a resistor structure that includes a layer of the etch-stop material, a layer of the metal fill material disposed over the etch-stop material layer, and a silicon material layer disposed over the metal fill material layer.