Polysilicon Resistor Layout for Leakage-Safe Compact ICs
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Solution Overview
Problem
As semiconductor devices shrink, the reduced spacing between circuit components leads to leakage currents, and increasing the spacing to prevent leakage currents enlarges the chip size.
Innovation Solution
Incorporation of polysilicon resistors on active regions and isolation layers in integrated circuits, with specific configurations to ensure identical overlap and cut patterns to prevent leakage currents while maintaining consistent resistance values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the spacing between circuit components is decreased to reduce chip size, then the chip size is reduced, but leakage current occurs between neighboring components
Solution Approach 1:
An isolation layer is introduced as an intermediary structure between adjacent active regions and well regions. This isolation layer acts as a mediator that electrically separates neighboring components, blocking leakage current paths while allowing the components to remain in close proximity, thus reducing chip size without sacrificing electrical isolation performance
Solution Approach 2:
The patent transitions from two-dimensional planar spacing to three-dimensional vertical stacking by placing polysilicon resistors above the isolation layer. This dimensional change allows circuit components to be arranged in multiple layers, increasing integration density while maintaining adequate spacing for leakage current prevention in the vertical dimension
2Object-generated harmful factors
If the spacing between circuit components is increased to prevent leakage current, then leakage current is prevented, but the chip size increases
Solution Approach 1:
The patent utilizes vertical stacking to arrange circuit components in multiple layers. Polysilicon resistors are positioned above the isolation layer in the vertical dimension, allowing horizontal spacing to be minimized while maintaining electrical isolation through the vertical isolation layer structure
Solution Approach 2:
The patent implements a nested structure where the isolation layer is positioned beneath the polysilicon resistors, and the polysilicon resistors are formed above the isolation layer. This nested arrangement allows compact integration of multiple functional elements in a vertically stacked configuration, maximizing space utilization while preventing leakage current
Data Source
AI summary
An integrated circuit includes active regions on an upper surface of a semiconductor substrate and having no electrical connection on the semiconductor substrate, an isolation layer on the upper surface of the semiconductor substrate and defining the active regions, and polysilicon resistors on the active regions and the isolation layer. The polysilicon resistors extend in a second direction that is perpendicular to a first direction in which the active regions extend, and are configured such that the number of active regions overlapping each of the polysilicon resistors in a vertical direction is identical.