Passive Polysilicon Resistor Structure for Precise Impedance Matching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional polysilicon resistors in semiconductor devices have low resistance, which is not suitable for precise impedance matching in analog and RF circuits, and single crystalline silicon resistors fail to provide adequate impedance matching.
Innovation Solution
A passive polysilicon device is integrated into the semiconductor substrate, featuring a polysilicon feature with embedded electrodes, and a method involving high k dielectric material layers, chemical mechanical polishing, and ion implantation to form precise resistance and impedance matching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional polysilicon resistors are used in scaled-down semiconductor devices, then the device can be manufactured with standard processes, but the resistance is too low to provide precise impedance matching for analog and RF circuits
Solution Approach 1:
The patent applies local quality by creating polysilicon regions with different doping concentrations within the same device structure. Specifically, the source and drain regions are heavily doped while the channel region maintains lower doping, enabling precise resistance control in the channel for impedance matching while keeping the overall fabrication process compatible with standard CMOS manufacturing
Solution Approach 2:
The patent utilizes parameter changes by varying the doping concentration in polysilicon regions to achieve desired resistance values. Through controlled ion implantation and thermal processing, the doping level is adjusted to precisely control the resistance of polysilicon resistors and the channel region, enabling accurate impedance matching for analog and RF applications
2Manufacturing precision
If single crystalline silicon resistors are used to increase resistance, then impedance matching improves, but the fabrication process becomes more complex and costly
Solution Approach 1:
The patent applies universality by designing a polysilicon-based device structure that serves multiple functions: it acts as both a transistor (with gate control) and provides precise resistance values for impedance matching. The same polysilicon layer forms both the active channel region and the resistor regions, eliminating the need for separate single crystalline silicon resistor fabrication processes
Solution Approach 2:
The patent uses copying by replicating the polysilicon device structure to create multiple resistors with different resistance values. By varying the geometric dimensions (length, width) and doping parameters of identical polysilicon-based structures, precise impedance matching is achieved across multiple circuit elements without requiring different fabrication processes
3Manufacturing precision
If polysilicon layer is heavily doped to increase resistance, then the resistance value increases, but the mobility of charge carriers decreases
Solution Approach 1:
The patent applies local quality by spatially separating the heavily doped source/drain regions from the channel region. The source and drain are heavily doped to provide good ohmic contacts and define the resistance, while the channel region maintains lower doping to preserve charge carrier mobility and enable effective gate control, thus resolving the trade-off between resistance control and carrier speed
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution allows for precise control of resistance and impedance matching, reducing fabrication costs while maintaining compatibility with high k dielectric and metal gate stacks, enhancing performance in analog and RF circuits.
Implementation Method 1
forming a high k dielectric material layer on a semiconductor substrate
Implementation Method 2
performing a first chemical mechanical polishing (CMP) process to etch back the ILD layer
Implementation Method 3
applying a first ion implantation to the semiconductor substrate to form electrodes embedded in the polysilicon feature
Data Source
AI summary
The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature.