Polysilicon Resistor Isolation Layout for Breakdown Reliability
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Solution Overview
Problem
Polysilicon resistors in integrated circuits are prone to failure due to dielectric breakdown caused by high electric field intensity, leading to conductive shorts, which can occur after the device is in service, posing reliability concerns for semiconductor manufacturers.
Innovation Solution
The solution involves forming isolation structures within a lightly doped semiconductor layer, rather than a heavily doped well region, to reduce electric field intensity and mitigate the effect of physical defects, thereby enhancing the reliability of polysilicon resistors by using a photomask design that excludes well implants under passive components, and implementing a semiconductor device structure with a dielectric isolation structure between doped layer portions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If isolation structures are formed in heavily doped well regions, then manufacturing is easier, but electric field intensity increases causing dielectric breakdown
Solution Approach 1:
The patent changes the doping concentration parameter of the semiconductor layer from heavily doped to lightly doped in the region where isolation structures are formed. This parameter change reduces electric field intensity at the isolation structure interfaces, preventing dielectric breakdown while maintaining manufacturing feasibility through standard lightly doped epitaxial growth processes.
2Adaptability or versatility
If polysilicon resistors are used in integrated circuits, then circuit functionality is achieved, but reliability decreases due to field failures
Solution Approach 1:
The patent introduces a lightly doped semiconductor layer as an intermediary between the polysilicon resistor and the substrate. This intermediate layer acts as a buffer that reduces electric field intensity, preventing dielectric breakdown at the polysilicon-substrate interface while maintaining the electrical functionality of the polysilicon resistor in the integrated circuit.
3Device complexity
If standard photolithographic masks are used, then manufacturing process is simpler, but well implants occur under passive components causing reliability issues
Solution Approach 1:
The patent applies local quality by designing the photomask to exclude well implant regions specifically under passive components such as polysilicon resistors, while allowing well implants in other regions of the substrate. This localized modification to the photomask design prevents harmful well implants under sensitive areas without significantly increasing overall device complexity or manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly increases the breakdown voltage of integrated circuits, reducing the likelihood of dielectric breakdown and conductive shorts, resulting in improved reliability and extended device lifetime.
Implementation Method 1
reduce electric field intensity and mitigate the effect of physical defects
Implementation Method 2
A dielectric isolation structure is located between the first and second layer portions
Data Source
AI summary
The present disclosure introduces, among other things, an electronic device, e.g. an integrated circuit (IC). The IC includes a semiconductor substrate comprising a first doped layer of a first conductivity type. A second doped layer of the first conductivity type is located within the first doped layer. The second doped layer has first and second layer portions with a greater dopant concentration than the first doped layer, with the first layer portion being spaced apart from the second layer portion laterally with respect to a surface of the substrate. The IC further includes a lightly doped portion of the first doped layer, the lightly doped portion being located between the first and second layer portions. A dielectric isolation structure is located between the first and second layer portions, and directly contacts the lightly doped portion.