Polysilicon Resistor Layout for Current Sense Accuracy
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Solution Overview
Problem
Current sensing in wireless power systems faces inaccuracies due to the piezoresistive effect in polysilicon resistors, which are subject to internal stresses during fabrication, leading to errors in high-accuracy environments, particularly at 1 amp of current where 1 milliamp corresponds to 0.1% error, consuming 20% of the 0.5% error margin.
Innovation Solution
The integrated circuit incorporates a current sense circuit with polysilicon resistors arranged symmetrically about an axis and at the same distance from the chip edge to minimize stress differential and resistance changes due to piezo resistivity, reducing errors without requiring post-fabrication calibration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If polysilicon resistors are used in current sensing, then the device can be manufactured with standard CMOS processes, but the piezoresistive effect introduces measurement errors in high-accuracy environments
Solution Approach 1:
The patent applies asymmetry in reverse - it uses symmetry strategically. The polysilicon resistors are arranged symmetrically about a central axis and positioned at equal distances from the chip edge, creating a balanced stress distribution that minimizes piezoresistive effects. This symmetric arrangement ensures that stress differentials cancel out, improving measurement precision while maintaining standard CMOS manufacturability
Solution Approach 2:
The patent changes the physical arrangement parameters of the resistors - specifically their positions and orientations relative to the chip edges and to each other. By positioning resistors at specific symmetric locations and angles, the design exploits geometric parameter optimization to minimize stress-induced resistance changes, thereby improving current sensing accuracy without altering the polysilicon material or fabrication process
2Measurement precision
If post-fabrication calibration is performed to correct resistor errors, then measurement precision improves, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent performs preliminary action by designing the resistor layout to inherently minimize piezoresistive effects before fabrication. The symmetric arrangement about the central axis and equal positioning from chip edges are built into the mask design, pre-compensating for stress effects. This eliminates the need for post-fabrication calibration, reducing device complexity and manufacturing cost while maintaining high measurement precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration achieves accuracy within 0.5% across a wide range of currents, minimizing the impact of piezoresistive effects and maintaining precision in current measurement.
Implementation Method 1
Current sensing in wireless power systems faces inaccuracies due to the piezoresistive effect in polysilicon resistors, which are subject to internal stresses during fabrication
Data Source
AI summary
One or more layout techniques may be used to balance a current sense circuit. The current sense circuit may include upstairs resistors for an amplifier which are formed of polysilicon material. The upstairs resistors may be arranged symmetrically about one or more stress gradients for improving an accuracy of the current sense circuit. The stress gradients may include stress gradients about an axis and stress gradients from a die edge.