Polysilicon Resistor Orientation for Trim Stability
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Solution Overview
Problem
The oscillation frequency of on-chip oscillators in semiconductor devices varies due to manufacturing errors and changes during the mold package process, making it difficult to maintain the required property of polysilicon resistors after trimming.
Innovation Solution
Polysilicon resistors are arranged in a direction perpendicular to the chip side, within specific areas and distances from the chip side, to minimize variations caused by the mold package process, ensuring the oscillation frequency remains accurate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If polysilicon resistors are arranged in conventional positions for trimming, then the resistance value can be adjusted during wafer fabrication, but the adjusted property varies after mold package process
Solution Approach 1:
The patent applies local quality by specifically positioning polysilicon resistors in the central region of the chip, away from peripheral stress concentration areas. This localized placement strategy ensures that the trimming resistors experience minimal mechanical stress during packaging, thereby maintaining their adjusted resistance values without variation after the mold package process.
Solution Approach 2:
The patent implements preliminary action by performing resistance value trimming during wafer fabrication before the mold package process. By completing the adjustment of resistance values in advance when the wafer is still in a stable state, the system establishes the desired electrical properties before any packaging-induced stress can affect the resistors.
2Measurement precision
If trimming is performed during wafer fabrication, then oscillation frequency accuracy can be adjusted, but the adjusted frequency varies after resin-sealing
Solution Approach 1:
The patent applies local quality by specifically positioning polysilicon resistors in the central region of the chip, away from peripheral stress concentration areas. This localized placement strategy ensures that the trimming resistors experience minimal mechanical stress during packaging, thereby maintaining their adjusted resistance values without variation after the mold package process.
Solution Approach 2:
The patent implements preliminary action by performing resistance value trimming during wafer fabrication before the mold package process. By completing the adjustment of resistance values in advance when the wafer is still in a stable state, the system establishes the desired electrical properties before any packaging-induced stress can affect the resistors.
3Area of stationary object
If diffused resistors are placed near the periphery for compact layout, then chip area is reduced, but resistance value varies due to piezo-resistance effect
Solution Approach 1:
The patent applies local quality by specifically positioning polysilicon resistors in the central region of the chip, away from peripheral stress concentration areas. This localized placement strategy ensures that the trimming resistors experience minimal mechanical stress during packaging, thereby maintaining their adjusted resistance values without variation after the mold package process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This arrangement maintains the adjusted oscillation frequency property of the functional circuit after the mold package process, reducing variations to within ±1% over a wide range of power supply voltages and temperatures.
Implementation Method 1
it is known that a value of a diffused resistor mounted in a semiconductor device varies after a mold package process for resin-sealing a chip. Japanese Unexamined Patent Publication No. 1998-189875 (Patent Document 1) discloses that, in order to suppress a variation in a resistance value of a diffused resistor formed by introducing impurities into a silicon substrate, the variation being caused by a piezo-resistance effect
Data Source
AI summary
Disclosed is a semiconductor device. The semiconductor device includes a functional circuit having a resistor formed by a plurality of polysilicon resistors, and in which the property of the functional circuit can be adjusted by trimming the resistor, and in which the polysilicon resistors are coupled in series or in parallel to each other and arranged in a direction perpendicular to one side of the semiconductor device.


