Vertically Offset Polysilicon Resistor for High-Voltage Sensing
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Solution Overview
Problem
Conventional high-voltage power switches in electronic devices face issues with voltage sensing using discrete resistors, which incur additional manufacturing costs and suffer from mismatch problems, and integrated thin film resistors may experience device breakdown due to concentrated electrical fields.
Innovation Solution
An ultra-high voltage polysilicon resistor is integrated with a lateral diffusion field-effect transistor (LDFET) in a spiral layout, providing a graded voltage drop and reducing electrical field concentration, along with a vertically offset design to optimize breakdown voltage and hot carrier injection effects, and a polysilicon resistor is used in a voltage divider circuit for accurate voltage sensing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If discrete resistors are used for voltage sensing, then voltage sensing capability is provided, but manufacturing cost increases and mismatch problems occur
Solution Approach 1:
The patent merges the voltage sensing resistor with the power switch device by forming the resistor within the same semiconductor structure. The polysilicon resistor is integrated into the drift region of the LDFET, eliminating the need for separate discrete resistors and reducing mismatch problems between sensing and power components.
Solution Approach 2:
The drift region of the LDFET serves dual purposes: it functions as the active switching region for high-voltage operation and simultaneously serves as the substrate for forming the voltage sensing resistor. This multi-functional design reduces component count and manufacturing complexity.
2Device complexity
If thin film resistors are integrated with the power switch, then device integration is improved, but device breakdown occurs due to concentrated electrical fields
Solution Approach 1:
The patent transitions from planar thin film resistors to a vertically-offset polysilicon resistor structure. The resistor is formed with its bottom surface offset vertically from the top surface of the LOCOS region, creating a three-dimensional configuration that distributes the electrical field more evenly and prevents concentration at specific points.
Solution Approach 2:
The patent changes the material parameter from thin film resistor material to polysilicon, and adjusts the geometric parameter by offsetting the resistor vertically. This creates a graded voltage drop across the resistor structure, reducing peak electrical field strength and preventing breakdown while maintaining integration.
3Ease of manufacture
If polysilicon resistor is formed directly on LOCOS region, then manufacturing process is simplified, but electrical field concentration occurs leading to breakdown
Solution Approach 1:
The patent introduces a vertical offset between the polysilicon resistor and the LOCOS region top surface. The resistor bottom surface is positioned at a different vertical level, creating a stepped configuration that simplifies the manufacturing process while distributing the electrical field to prevent breakdown.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution improves the reliability and performance of high-voltage power switches by reducing the likelihood of device breakdown, enhancing self-protected electrostatic discharge, and minimizing RC time constant delay for improved system performance at high frequencies.
Implementation Method 1
provides a graded voltage drop and reducing electrical field concentration
Implementation Method 2
optimize breakdown voltage and hot carrier injection effects
Implementation Method 3
a polysilicon resistor is used in a voltage divider circuit for accurate voltage sensing
Data Source
AI summary
A semiconductor device includes an active region, a LOCOS region formed within the active region and that extends vertically above a top surface of the active region, a gate region formed above the top surface of the active region, and a polysilicon resistor having a bottom surface that is offset vertically and physically isolated from a top surface of the LOCOS region. The active region includes a source region laterally disposed from the gate region, a drain region laterally disposed from the gate region, and a drift region laterally disposed between the gate region and the drain region. The polysilicon resistor is formed above the drift region. The active region further includes a first charge balance region formed in the active region below the drift region.