Polysilicon Ring Transistor Layout for Inkjet Printhead Area Reduction
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Solution Overview
Problem
Inkjet printing devices using the no-field oxide process face inefficiencies in transistor layout, leading to increased semiconductor area requirements, higher costs, and reduced electrical speed due to the lack of field oxide isolation, which complicates the layout and reduces packing density.
Innovation Solution
The implementation of a partially etched gate NMOS transistor process, where a polysilicon ring is used to form doped regions and then partially etched to conserve silicon area and reduce manufacturing costs, allowing for a more efficient transistor layout with higher packing density and increased electrical speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If field oxide isolation is used for transistor layout, then electrical speed and packing density are improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent removes the field oxide isolation layer from the transistor layout, extracting only the essential gate structure components. This eliminates the complex multi-layer field oxide isolation process while maintaining adequate electrical performance through optimized gate geometry and spacing.
Solution Approach 2:
The patent applies local quality optimization by concentrating isolation efforts only where absolutely necessary - at the gate edges and critical transistor boundaries - rather than using comprehensive field oxide isolation across the entire device area. This localized approach reduces manufacturing steps while preserving electrical speed in critical regions.
2Area of moving object
If field oxide isolation is used for transistor layout, then packing density is improved, but manufacturing cost and process complexity increase
Solution Approach 1:
The patent extracts and eliminates the field oxide isolation process steps, reducing manufacturing complexity and cost. The simplified layout achieves adequate packing density through optimized gate structure placement and spacing without requiring the additional fabrication steps associated with field oxide formation and patterning.
Solution Approach 2:
The patent applies partial isolation actions only at critical transistor boundaries and gate edges rather than comprehensive field oxide coverage. This partial approach achieves sufficient packing density for the application while significantly reducing manufacturing cost and process complexity compared to full field oxide isolation.
3Ease of manufacture
If no-field oxide process is used, then manufacturing cost is reduced, but transistor layout efficiency and electrical speed decrease
Solution Approach 1:
The patent applies local quality enhancement by implementing optimized gate edge geometry and selective spacing only at critical transistor regions. This localized optimization maintains electrical speed performance in the no-field oxide process by concentrating isolation effects where they are most needed - at gate boundaries and adjacent transistor interfaces - without requiring comprehensive field oxide isolation.
Solution Approach 2:
The patent changes geometric parameters of the gate structure and transistor spacing to compensate for the absence of field oxide isolation. By optimizing gate width, length, and spacing parameters, the design achieves adequate electrical speed performance in the simplified no-field oxide process.
4Ease of manufacture
If no-field oxide process is used, then manufacturing cost is reduced, but layout complexity and area requirements increase
Solution Approach 1:
The patent applies local quality optimization by implementing enhanced spacing and isolation only at critical transistor boundaries and gate edges. This localized approach achieves adequate layout efficiency and packing density in the no-field oxide process by concentrating design efforts where they are most needed, rather than requiring uniform spacing across the entire chip area.
Solution Approach 2:
The patent optimizes geometric parameters including gate dimensions, transistor spacing, and layout arrangement to maximize packing density in the no-field oxide process. These parameter adjustments compensate for the lack of field oxide isolation, achieving efficient area utilization without increasing overall semiconductor area requirements.
Data Source
Figure 1
Figure 2A~2C
Figure 3A~4B
AI summary
A semiconductor device and method of forming the same is described. In an example, a polysilicon layer is deposited on a substrate having at least one polysilicon ring. The substrate is doped using the polysilicon layer as a mask to form doped regions in the substrate. A dielectric layer is deposited over the polysilicon layer and the substrate. The dielectric layer is etched to expose portions of the polysilicon layer. A metal layer is deposited on the dielectric layer. The metal layer, the dielectric layer, and the exposed portions of the polysilicon layer are etched such that at least a portion of each polysilicon ring is removed.