Polysilicon Ring Structures for Trench MOSFET Gate Integrity
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Solution Overview
Problem
MOSFET devices face performance issues due to thinning of gate dielectric layers in certain areas, leading to gate oxide integrity problems, particularly at the top and bottom portions of trenches, which can be exacerbated by manufacturing processes and device layouts.
Innovation Solution
The implementation of a polysilicon layer with a polysilicon ring configuration around the end portions of trenches, where the trench ends are disposed below an opening in the polysilicon layer, effectively addressing thinning issues by minimizing resistance and maintaining gate integrity through strategic polysilicon coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional trench layouts are used, then device manufacturing is simpler, but gate dielectric layers thin out at trench end portions leading to gate oxide integrity issues
Solution Approach 1:
The polysilicon layer is segmented into regions with different configurations: some trenches have end portions disposed below openings in the polysilicon layer, while other trenches have end portions disposed between sides of openings. This segmentation allows different trenches to be optimized for their specific functions, with some providing better gate oxide integrity through the below-opening configuration while others maintain simpler layouts.
Solution Approach 2:
Different portions of the polysilicon layer are given different local qualities - specifically, the polysilicon layer includes openings at certain locations where trenches have end portions below the openings to prevent thinning, while other areas maintain continuous polysilicon coverage. This local variation in polysilicon configuration addresses the gate dielectric thinning problem specifically at critical trench end portions without unnecessarily complicating the entire device structure.
2Ease of manufacture
If gate dielectric layers are thinned due to manufacturing processes, then manufacturing may be easier, but device performance deteriorates
Solution Approach 1:
The patent applies preliminary anti-action by configuring the polysilicon layer and trench structures in advance to prevent gate dielectric thinning before it occurs. The trench end portions are strategically positioned below openings in the polysilicon layer or between sides of openings, creating a structural arrangement that prevents the thinning effect from manifesting during subsequent manufacturing processes, thereby maintaining both ease of manufacture and device performance.
3Reliability
If polysilicon layer is added to address thinning, then gate oxide integrity improves, but manufacturing complexity increases
Solution Approach 1:
The polysilicon layer serves multiple functions simultaneously: it provides mechanical support, defines trench boundaries, controls gate dielectric thickness through its opening configuration, and establishes electrical connections. By making the polysilicon layer multi-functional, the patent reduces the need for additional separate structures or processes, thereby improving gate oxide integrity without proportionally increasing manufacturing complexity.
Data Source
AI summary
In a general aspect, an apparatus, can include a trench disposed within a semiconductor region of a substrate. The trench can be lined with a gate dielectric and including an electrode disposed within the trench. The apparatus can include a polysilicon layer disposed above the trench. The trench can have an end portion disposed below an opening in the polysilicon layer. The end portion of the trench can be disposed between a first side of the opening and a second side of the opening.