Polysilicon Rod Surface Treatment for Resistivity Uniformity
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Solution Overview
Problem
In the FZ method for producing large-diameter single crystal silicon, the unmelted part of the polysilicon rod causes uneven resistivity distribution due to impurities near the surface, leading to increased in-plane resistivity gradient (RRG) issues, which are exacerbated by the limited stirring effect and contamination during the CVD process.
Innovation Solution
A polysilicon rod with improved in-plane resistivity distribution is manufactured by subjecting the silicon core wire to surface treatment at temperatures not exceeding 1000°C, including wet etching and hydrogen halide etching within a controlled temperature range to minimize impurity elution and oxide film formation, ensuring uniform resistivity distribution during the FZ method.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the diameter of the single crystal is increased, then the production capacity is improved, but the unmelted part remains in the polysilicon rod causing uneven resistivity distribution
Solution Approach 1:
The invention changes the physical-chemical parameters of the polysilicon rod surface by controlling the temperature during CVD process (not exceeding 1000°C) and using specific etching treatments to modify the surface state, thereby preventing impurity incorporation and ensuring uniform resistivity distribution even in large-diameter single crystals
Solution Approach 2:
The invention performs preliminary surface treatment on the silicon core wire before CVD deposition, including etching to remove damaged layers and impurities, and controlling the initial temperature to prevent oxide film formation. This preliminary action ensures that the starting surface is clean and free from contaminants that would cause uneven resistivity in the final large-diameter single crystal
2Manufacturing precision
If wet etching is performed to remove damaged layer and impurities, then the surface quality is improved, but re-contamination and natural oxide film formation occur during storage
Solution Approach 1:
The invention maintains continuous protection of the silicon core wire surface by performing etching immediately before CVD deposition without intermediate storage, and by controlling the CVD process to begin immediately after etching. This eliminates the time gap where re-contamination and oxide formation would occur, maintaining surface quality throughout the process
Solution Approach 2:
The invention uses an inert or controlled atmosphere during the etching and CVD process to prevent oxidation and contamination of the silicon core wire surface. By maintaining a protective atmosphere throughout the process, the surface remains clean and free from natural oxide film formation
3Speed
If the temperature is increased to improve melting efficiency, then the processing speed is improved, but impurity elution from the silicon core wire increases
Solution Approach 1:
The invention optimizes the temperature parameter by setting it to not exceed 1000°C during CVD deposition. This temperature control prevents excessive impurity elution from the silicon core wire while still allowing sufficient melting and deposition efficiency, achieving a balance between processing speed and material purity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method achieves a high-purity polysilicon rod with reduced RRG, maintaining high resistance and uniform resistivity distribution, even at larger diameters, thereby enhancing the quality of single crystal silicon produced by the FZ method.
Implementation Method 1
deposition of chlorosilane gas as a raw material in the air by using Joule heat generated when a current flows through a silicon rod (silicon core wire) disposed in an electrode
Implementation Method 2
a polysilicon rod 1a is inductively heated by a coil 4, melting occurs on the surface of the polysilicon rod 1a
Implementation Method 3
The silicon core wire used in the CVD method is cleaned by wet etching (typically nitric acid/hydrogen fluoride) for the purpose of removing a damaged layer
Data Source
AI summary
A polysilicon rod has a diameter of 120 mm or more, the polysilicon rod having a lowest resistivity of 3300 Ωcm or more and an RRG of 100% or less. A polysilicon rod has a diameter of 140 mm or more, the polysilicon rod having a lowest resistivity of 3300 Ωcm or more and an RRG of 150% or less.