Polysilicon Scaling for Flash Memory Capacitance Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional memory manufacturing processes lack control over core and peripheral polysilicon line thickness, leading to uniformity issues and increased capacitance between memory cells, which affects the performance and yield of flash-based memories.
Innovation Solution
The process involves forming a layered stack with a thinner core polysilicon layer and a thicker peripheral polysilicon layer, isolating the core section from the peripheral polysilicon, and patterning polysilicon lines to create word, source, and drain select gate lines, allowing for independent optimization of core and peripheral polysilicon, reducing capacitance, and improving yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a uniform polysilicon layer is used for both core and peripheral sections, then the manufacturing process is simpler, but the polysilicon line thickness cannot be independently optimized leading to uniformity issues and increased capacitance
Solution Approach 1:
The polysilicon structure is segmented into two distinct layers: a first polysilicon layer for core memory cells and a second polysilicon layer for peripheral devices. This segmentation allows independent thickness optimization - the first layer can be made thinner to reduce capacitance in the core array, while the second layer can be made thicker to provide sufficient conductivity for peripheral devices, thereby resolving the uniformity issue without excessive complexity
Solution Approach 2:
Different polysilicon line thicknesses are applied to different functional regions: thinner polysilicon lines in the core memory cell array to reduce capacitance and improve speed, and thicker polysilicon lines in the peripheral device region to ensure adequate electrical conductivity. This local differentiation optimizes performance for each specific function while maintaining overall device integration
2Reliability
If thicker polysilicon lines are used to improve conductivity, then electrical performance improves, but capacitance between memory cells increases affecting performance
Solution Approach 1:
The polysilicon conductive paths are segmented into two thickness regimes: thinner polysilicon (first layer) for core memory cell interconnections to minimize capacitance, and thicker polysilicon (second layer) for peripheral device connections where high conductivity is critical. This segmentation enables simultaneous optimization of both conductivity and capacitance reduction
Solution Approach 2:
The thickness parameter of the polysilicon layer is changed based on functional requirements: the first polysilicon layer is formed with a thickness optimized for low-capacitance core connections, while the second polysilicon layer is formed with a greater thickness optimized for high-conductivity peripheral connections, thereby resolving the contradiction between conductivity and capacitance
3Manufacturing precision
If separate polysilicon layers are formed for core and peripheral sections, then independent optimization is achieved, but the manufacturing process complexity increases
Solution Approach 1:
The manufacturing process is segmented into sequential deposition steps: first polysilicon layer formation, then second polysilicon layer formation. While this adds a process step, each layer can be independently optimized and controlled, achieving superior thickness uniformity and functional performance that justifies the additional manufacturing complexity
Solution Approach 2:
The dual-layer polysilicon structure serves multiple functions simultaneously: the first layer provides low-capacitance interconnects for core memory cells, while the second layer provides high-conductivity connections for peripheral devices. This multi-functionality is achieved through a single integrated manufacturing process that deposits both layers in sequence, optimizing both core and peripheral performance without requiring separate manufacturing lines
Data Source
AI summary
A memory and method of manufacture employing word line scaling. A layered stack, including a charge trapping component and a core polysilicon layer, is formed on a core section and a peripheral section of a substrate. A portion of the layered stack, including the core polysilicon layer is then removed from the peripheral section. A peripheral polysilicon layer, which is thicker than the core polysilicon layer of the layered stack, is next formed on the layered stack and the peripheral section. The layered stack is then isolated from the peripheral polysilicon layer by removing a portion of the peripheral polysilicon layer from the core section, and polysilicon lines are patterned in the isolated layered stack.