Polycrystalline Silicon Separator Layer for RF Structures
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Solution Overview
Problem
Existing methods for fabricating structures for high-frequency applications require intermediate treatments like plasma treatment to maintain resistivity, which can be costly and inefficient, especially when dealing with polycrystalline silicon separator layers in RF applications.
Innovation Solution
Forming a polycrystalline silicon separator layer with an entirely random grain orientation over a significant portion of its thickness, allowing for higher temperature strengthening annealing without transforming it into monocrystalline silicon, using vapour phase chemical deposition and thermal oxidation to achieve optimal thickness and grain size for enhanced RF performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If intermediate treatments like plasma treatment are applied to strengthen the interface, then the cohesion of the structure is improved, but the process complexity and cost increase
Solution Approach 1:
The invention extracts and eliminates the intermediate plasma treatment step from the fabrication process. By designing the separator layer with specific polycrystalline silicon properties (random grain orientation, controlled thickness), the interface strength is achieved directly through the separator layer design rather than through additional intermediate treatments, thereby reducing process complexity while maintaining interface cohesion.
2Strength
If strengthening annealing is performed at high temperature for extended duration, then the mechanical strength of the structure is improved, but the polycrystalline silicon transforms into monocrystalline silicon reducing resistivity
Solution Approach 1:
The invention changes the parameters of the separator layer, specifically its thickness (5-50 nm) and grain orientation (random polycrystalline structure), to create a configuration that can withstand high-temperature strengthening annealing (above 950°C) without transforming into monocrystalline silicon. The random grain orientation and controlled thickness prevent the formation of large monocrystalline regions, thereby maintaining resistivity while achieving mechanical strength through the annealing process.
3Strength
If the heat budget during annealing is increased to strengthen the structure, then the mechanical strength is improved, but the polycrystalline silicon transforms into monocrystalline silicon
Solution Approach 1:
The invention modifies the separator layer parameters (thickness of 5-50 nm and random grain orientation) to increase the thermal stability of the polycrystalline structure. This configuration raises the threshold for transformation into monocrystalline silicon, allowing the structure to endure high heat budgets during annealing for mechanical strengthening while preserving the polycrystalline composition and associated electrical properties.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables increased heat budgets during annealing without transforming the separator layer, improving mechanical strength and RF performance by governing second-harmonic generation and maintaining satisfactory resistivity for RF applications, while eliminating the need for intermediate treatments.
Implementation Method 1
subjecting the structure to a strengthening annealing of at least 10 minutes after the step g), the strengthening annealing being executed during the step h) at a temperature strictly greater than 950°C
Implementation Method 2
The step d1) of vapour phase chemical deposition of the separator layer, at atmospheric pressure, and with a deposition temperature of between 800°C and 1050°C
Implementation Method 3
using vapour phase chemical deposition and thermal oxidation to achieve optimal thickness and grain size for enhanced RF performance
Data Source
Figure 1A~1G
Figure 2~4
AI summary
This method for fabricating a structure (3) comprising, in succession, a support substrate (2), a dielectric layer (10), an active layer (11), a separator layer (20) of polycrystalline silicon, comprises the steps of: a) providing a donor substrate, b) forming an embrittlement area in the donor substrate, c) providing the support structure (2), d) forming the separator layer (20) on the support substrate (2), e) forming the dielectric layer (10), f) assembling the donor substrate (1) and the support substrate (2),. g) fracturing the donor substrate (1) along the embrittlement area, h) subjecting the structure (3) to a strengthening annealing of at least 10 minutes, the fabrication method being noteworthy in that the step d) is executed in such a way that the polycrystalline silicon of the separator layer (20) exhibits an entirely random grain orientation, and in that the strengthening annealing is executed at a temperature strictly greater than 950 °C and less than 1200 °C.