Polycrystalline Silicon Layer Width Control via Side Wall Mask
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor device manufacturing methods struggle to form impurity-doped polycrystalline silicon layers with sufficiently narrow widths due to alignment precision limitations in photolithography, leading to poor leak current characteristics and variability.
Innovation Solution
A method involving the formation of a mask layer and a side wall on the polycrystalline silicon layer, where the mask layer and side wall are used to dope and etch the layer, allowing for self-aligned control of the impurity-doped layer width, independent of photolithography precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photolithography alignment is used to determine impurity-doped layer width, then the manufacturing process is simple, but the layer width cannot be sufficiently narrow and has large variation
Solution Approach 1:
A mask layer is formed on the polycrystalline silicon layer before impurity doping. Side walls are then formed on the side faces of the mask layer, extending along the thickness direction. These side walls serve as preliminary structures that define the width of the impurity-doped region, allowing precise control independent of photolithography alignment precision.
Solution Approach 2:
The mask layer and side walls act as intermediary structures between the photolithography process and the final impurity-doped layer. The side walls, formed on the mask layer, mediate the width definition by providing physical boundaries that constrain the impurity doping region, thereby achieving narrow and precise layer widths without relying on alignment precision.
2Reliability
If the impurity-doped polycrystalline silicon layer width is increased to compensate for alignment errors, then manufacturing is easier, but leak current characteristics deteriorate
Solution Approach 1:
The mask layer is formed with a width larger than the desired final doped region, and side walls are formed on its side faces. During impurity doping, the side walls act as barriers that prevent impurity diffusion beyond a controlled width, ensuring that the final doped region has precise width control and narrow dimensions necessary for good leak current characteristics.
Solution Approach 2:
The side walls serve as intermediary barriers that mediate between the mask layer and the impurity doping process. They physically constrain the impurity diffusion region to a narrow width defined by the side wall spacing, thereby achieving both narrow layer width and reliable leak current characteristics simultaneously.
3Manufacturing precision
If conventional etching is used after resist mask formation, then the process is simple, but the hetero semiconductor region width cannot be sufficiently narrow
Solution Approach 1:
Side walls are formed on the side faces of the mask layer before the etching process. These side walls extend along the thickness direction and serve as preliminary etch masks that define the width of the hetero semiconductor region. During etching, the side walls protect the underlying polycrystalline silicon layer, ensuring a narrow etched region with precise width control.
Solution Approach 2:
The side walls act as intermediary etch masks that mediate between the original resist mask and the etching process. They provide precise width definition for the etched hetero semiconductor region by serving as physical barriers during etching, achieving narrow region widths that are independent of photolithography alignment precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of narrow impurity-doped polycrystalline silicon layers with improved leak current characteristics and reduced variability, enhancing device performance by allowing for precise control of the layer width and increasing breakdown voltage.
Implementation Method 1
forming a side wall that is provided on a side face of the mask layer and covers part of the polycrystalline silicon layer
Implementation Method 2
doping an impurity into the polycrystalline silicon layer by using at least one of the mask layer and the side wall as a mask; and etching the polycrystalline silicon layer by using at least one of the mask layer and the side wall as a mask
Data Source
AI summary
A method of manufacturing a semiconductor device having a polycrystalline silicon layer (5) includes; a step of forming a mask layer (7) on the polycrystalline silicon layer (5); a step of forming a side wall (8) that is provided on a side face of the mask layer (7) and covers part of the polycrystalline silicon layer (6); a step of doping an impurity (52) into the polycrystalline silicon layer (5) by using at least one of the mask layer (7) and the side wall (8) as a mask; and a step of etching the polycrystalline silicon layer (5, 6) by using at least one of the mask layer (7) and the side wall (8) as a mask.