Polysilicon Sidewall Spacer Multi-Bit NVM Cell
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Solution Overview
Problem
Current multi-bit non-volatile memory (NVM) cells face challenges in manufacturing due to electron mobility issues in polysilicon floating gates, which prevent effective storage of electrons near specific source/drain regions, making them less manufacturable compared to nitride or nanocrystal-based solutions.
Innovation Solution
The implementation of sidewall spacers made of polysilicon as floating gates adjacent to source/drain regions, with a control gate stack and dielectric layer, allows for the formation of two distinct storage areas per memory cell, enabling effective electron storage and control for multi-bit operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If polysilicon floating gates are used for multi-bit NVM cells, then manufacturability is improved, but electron mobility causes electrons to move within the polysilicon layer preventing maintenance near specific source/drain regions
Solution Approach 1:
The patent divides the storage function into two separate polysilicon layers: a first polysilicon layer for storing first electrons near the first source/drain region, and a second polysilicon layer for storing second electrons near the second source/drain region. This segmentation prevents electron mixing and maintains reliable multi-bit storage while using manufacturable polysilicon materials.
Solution Approach 2:
The patent transitions from a single-layer polysilicon floating gate to a multi-layer structure with first and second polysilicon layers positioned at different vertical dimensions. This dimensional separation allows electrons to be confined to specific layers near their respective source/drain regions, solving the electron mobility problem while maintaining manufacturability.
2Reliability
If nitride or nanocrystals are used for storage, then electron immobility is achieved, but manufacturing provenness is reduced
Solution Approach 1:
The patent changes the structural parameters of the polysilicon floating gate from a single layer to multiple layers with different thicknesses and positions. By adjusting the thickness of the first polysilicon layer relative to the second, the patent achieves electron confinement similar to nitride or nanocrystals while maintaining the manufacturability advantages of polysilicon.
Data Source
AI summary
A multi-bit non volatile memory cell includes a first floating gate sidewall spacer structure and a second floating gate sidewall spacer structure physically separated from the first floating gate sidewall spacer structure. Each floating gate sidewall spacer structure stores charge for logically storing a bit. The floating gate sidewall spacer structures are formed adjacent to a patterned structure by sidewall spacer formation processes from a layer of floating gate material (e.g. polysilicon). A control gate is formed over the floating gate sidewall spacer structures by forming a layer of control gate material and then patterning the layer of control gate material.