Polysilicon Spacer Isolation for SOI Floating Body Cells
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Solution Overview
Problem
Conventional methods for fabricating semiconductor devices with floating body cells on SOI substrates face challenges in maintaining sufficient data retention, hole storage capability, and punch characteristics while minimizing dielectric leakage and parasitic transistor interference between adjacent cells.
Innovation Solution
The solution involves forming gate patterns over a silicon-on-insulator substrate with polysilicon spacers containing a second-conductivity type dopant, which are extended from the buried insulation layer to the gate patterns and silicon bodies, and metal contact plugs between adjacent polysilicon spacers to isolate memory cells, eliminating parasitic effects and ensuring sufficient hole storage capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-concentration ions are implanted into sources and drains to isolate memory cells, then cell isolation is improved, but punch characteristics of the buried insulation layer are degraded
Solution Approach 1:
The patent introduces a polysilicon layer as an intermediary substance between adjacent memory cells. This polysilicon layer is selectively removed to form isolation regions, serving as a mediator that achieves cell isolation without requiring high-concentration ion implantation that would damage the buried insulation layer's punch characteristics.
Solution Approach 2:
The patent changes the approach from modifying electrical parameters (high-concentration ion implantation) to structural parameters (polysilicon layer formation and selective removal). By changing the isolation mechanism from electrical to structural, the punch characteristics are preserved while achieving effective cell isolation.
2Reliability
If the thickness of silicon layer is reduced to isolate cells, then cell isolation is improved, but hole storage capability is reduced
Solution Approach 1:
The patent segments the silicon layer by selectively removing portions to form isolation regions between cells. This segmentation achieves cell isolation while preserving the silicon layer thickness in the active cell regions, thereby maintaining hole storage capability. The silicon layer is divided into functional zones: isolation regions (removed) and active regions (retained for hole storage).
Solution Approach 2:
The patent applies different treatments to different locations: the silicon layer is removed in isolation regions between cells but maintained at full thickness in active cell regions. This local differentiation achieves cell isolation where needed while preserving hole storage capability where required.
3Productivity
If floating body cells are formed over the same active region, then device density is improved, but data interference between adjacent cells occurs due to parasitic transistors
Solution Approach 1:
The patent uses a polysilicon-based isolation structure as an intermediary to separate adjacent floating body cells. This mediator eliminates the parasitic transistor formation between cells while allowing both cells to share the same active region, thus achieving high device density without data interference.
4Ease of manufacture
If conventional junction-based isolation is used, then manufacturing process is simplified, but reliability is degraded due to parasitic bipolar transistors
Solution Approach 1:
The patent introduces a polysilicon layer as an intermediary that replaces the conventional junction-based isolation. This polysilicon-based isolation mechanism eliminates parasitic bipolar transistor formation while maintaining manufacturing simplicity through standard deposition and etching processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively isolates adjacent memory cells, improves punch characteristics, and maintains sufficient hole storage capability without requiring high concentration ion implantation, thereby reducing data interference and leakage current.
Implementation Method 1
a plurality of polysilicon spacers, each formed over a sidewall of the silicon bodies and each containing a second-conductivity type dopant
Implementation Method 2
a contact plug electrically connected to at least one of the polysilicon spacers
Data Source
AI summary
A semiconductor device and a method for fabricating the same. A plurality of gate patterns are formed over a first-conductivity type silicon layer of a silicon-on-insulator semiconductor substrate including a buried insulation layer, so as to be separated from each other. A plurality of silicon bodies are formed under the gate patterns, by removing a portion of the first-conductivity type silicon layer exposed between the gate patterns. A plurality of polysilicon spacers are formed over a sidewall of the silicon bodies, and each contains a second-conductivity type dopant. A contact plug is electrically connected to at least one of the polysilicon spacers.