Polysilicon Stack Collector Structure for RF Parasitic Capacitance Reduction

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Solution Overview

Problem

Conventional SiGe HBTs face difficulties in reducing parasitic capacitance between pseudo buried layers and the substrate, which affects RF power characteristics due to shallow junctions and high doping concentrations.

Innovation Solution

A structure for picking up a collector region is formed with polysilicon stacks, comprising an undoped polysilicon layer and a doped polysilicon layer of opposite conductivity type, where the doped polysilicon layer has a depth sufficient to reduce parasitic capacitance, and an optional intermediate layer prevents impurity diffusion, allowing for a depletion region and improved ohmic contact.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If pseudo buried layers are formed with high doping concentration to improve conductivity, then electrical conductivity is improved, but parasitic capacitance increases

Engineering Contradiction:
Improveelectrical conductivityVSAvoidparasitic capacitance
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The collector region is divided into multiple segments: the original collector region, and multiple collector extension regions extending into the isolation regions. This segmentation allows the high-doping collector region to be separated from the substrate by low-doping extension regions, reducing parasitic capacitance while maintaining conductivity where needed.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different doping concentrations are applied to different regions: high doping concentration in the collector region for conductivity, and low doping concentration in the collector extension regions for capacitance reduction. This local quality differentiation resolves the contradiction between conductivity and parasitic capacitance.

Inventive Principle:
Principle #3Local quality

2Object-affected harmful factors

If collector region depth is increased to reduce parasitic capacitance, then parasitic capacitance decreases, but manufacturing complexity increases

Engineering Contradiction:
Improveparasitic capacitanceVSAvoidmanufacturing complexity
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The collector extension regions are formed by merging the collector region formation process with the isolation region structure. The extension regions naturally extend into the isolation regions during the same doping process, avoiding separate manufacturing steps and reducing complexity.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The isolation regions are formed first with sufficient depth before the collector region is formed. This preliminary action allows the collector extension regions to automatically extend into the pre-formed isolation regions, simplifying the overall manufacturing process while achieving the desired capacitance reduction.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Significantly reduces parasitic capacitance and series resistance, enhancing RF characteristics by decreasing capacitance density by 53% and improving breakdown voltage, while maintaining a good ohmic contact.

Implementation Method 1

the undoped polysilicon layer serving as a depletion region between the doped polysilicon layer and the substrate

Methodology Applied
Scientific EffectDepletion region:

Implementation Method 2

improving ohmic contact

Methodology Applied
Scientific EffectOhmic contact:

Data Source

PatentUS9130003B2Structure for picking up a collector and method of manufacturing the same
Publication Date: 2015.09.08 SHANGHAI HUAHONG GRACE SEMICON MFG CORP
  • US9130003B2 patent drawing
  • US9130003B2 patent drawing
  • US9130003B2 patent drawing

AI summary

A structure for picking up a collector region including a pair of polysilicon stacks formed in the isolation regions and extending below the collector region; and a pair of collector electrodes contacting on the polysilicon stacks, wherein the pair of polysilicon stacks includes: an undoped polysilicon layer and a doped polysilicon layer located on the undoped polysilicon layer, wherein a depth of the doped polysilicon layer is greater than a depth of the collector region; the depth of the collector region is greater than a depth of the isolation regions.