Polysilicon Storage Dot Memory Cell for Scalability
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Solution Overview
Problem
Non-volatile floating gate memory cells with polysilicon storage dots face challenges in charge-trapping efficiency and retention due to poor scalability and intricate structure, especially as the channel length shrinks, leading to unreliable device performance.
Innovation Solution
A non-volatile floating gate memory cell design featuring two polysilicon storage dots spaced apart at the opposing lateral edges of the control gate and semiconductor substrate, with a method involving a gate oxide layer, polysilicon gate formation, tunnel oxide layer formation, and annealing to control oxidation and separate the dots, ensuring efficient charge storage and conduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If polysilicon storage dots are used in conventional SONOS memory cells, then charge-trapping efficiency is improved, but device reliability deteriorates due to poor scalability as channel length shrinks
Solution Approach 1:
The patent divides the storage function into two separate polysilicon dots positioned at opposite lateral edges of the control gate, rather than using a continuous trapping layer. This segmentation allows each dot to be independently controlled and positioned, improving scalability as channel length decreases while maintaining charge-trapping efficiency.
Solution Approach 2:
The patent transitions from a planar trapping structure to a three-dimensional configuration where polysilicon dots are positioned at vertical sidewalls of the control gate. This dimensional change allows the storage dots to be separated by the gate width rather than channel length, enabling better scalability as channel dimensions shrink.
2Productivity
If channel length is reduced to improve scaling, then device density is improved, but charge-trapping efficiency deteriorates due to punch-through of the trapping area
Solution Approach 1:
By positioning storage dots at the vertical sidewalls of the control gate rather than within the channel plane, the patent separates the storage function from the channel length dimension. The dots are separated by gate width instead of channel length, allowing channel length to be reduced for higher density without compromising charge-trapping efficiency.
Solution Approach 2:
The patent concentrates charge-trapping functionality at specific localized positions (the two vertical sidewalls of the control gate) rather than distributing it throughout the channel. This local concentration of trapping capability ensures reliable charge storage even as overall channel dimensions are reduced for scaling.
3Area of stationary object
If polysilicon dots are placed close together to improve density, then device area is reduced, but separation control becomes difficult leading to unreliable performance
Solution Approach 1:
The patent uses the control gate structure itself as the defining template for dot separation. The two polysilicon dots are positioned at the vertical sidewalls of the gate, meaning their separation is automatically determined by the gate width and thickness. This self-aligning approach eliminates the need for separate alignment processes and ensures consistent separation control.
Solution Approach 2:
The patent combines the formation of control gate and positioning of storage dots into a single integrated structure. The dots are formed concurrently with or relative to the gate structure, merging two previously separate fabrication steps into one unified process that inherently ensures proper spacing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances charge-trapping efficiency and retention by maintaining the separation of polysilicon dots as wide as the control gate, improving scalability and reliability of the memory cell, even as the channel length decreases.
Implementation Method 1
A tunnel oxide layer is conformably formed on the semiconductor substrate and the control gate
Implementation Method 2
an annealing cycle, performed using conventional furnace procedures or using a rapid thermal annealing procedure at a temperature between about 650 to 800° C., to form a silicon oxide layer and leave un-reacted polysilicon dots
Implementation Method 3
an annealing cycle... to form a silicon oxide layer and leave un-reacted polysilicon dots
Data Source
AI summary
Non-volatile floating gate memory cells with polysilicon storage dots and fabrication methods thereof. The non-volatile floating gate memory cell comprises a semiconductor substrate of a first conductivity type. A first region of a second conductivity type different from the first conductivity type is formed in the semiconductor substrate. A second region of the second conductivity type is formed in the semiconductor substrate spaced apart from the first region. A channel region connects the first and second regions for the conduction of charges. A dielectric layer is disposed on the channel region. A control gate is disposed on the dielectric layer. A tunnel dielectric layer is conformably formed on the semiconductor substrate and the control gate. Two charge storage dots are spaced apart from each other at opposing lateral edges of the sidewalls of the control gate and surface of the semiconductor substrate.