Low Resistance Polysilicon Strap for Memory Cell Density
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Solution Overview
Problem
In semiconductor memory manufacturing, the increased leakage in gate dielectrics due to shrinking process technologies requires the use of high-K metal gates, but memory devices still need polysilicon gates, posing challenges in forming low resistance contacts between polysilicon structures while maintaining process compatibility with logic devices.
Innovation Solution
A low resistance polysilicon strap is formed using a metal contact to polysilicon structures, with a sidewall spacer defining the Control Gate adjacent to the polysilicon Select Gate, and a salicide process creating a polycide strap, allowing for reduced spacing and improved density, and a mask is used to prevent poly strap removal during the CMP process, ensuring compatibility with High-K Metal Gate processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-K metal gate process is used to reduce dielectric leakage, then gate dielectric leakage is reduced, but polysilicon gate formation becomes incompatible with the process
Solution Approach 1:
The patent applies different gate structures to different device regions: high-K metal gates are used in logic devices to reduce leakage, while polysilicon gates are retained in memory devices where they are needed. This local differentiation resolves the contradiction by allowing each device type to use the most appropriate gate structure for its specific requirements.
Solution Approach 2:
The semiconductor structure is segmented into different regions with different gate configurations. The logic portion uses high-K metal gates while the memory portion uses polysilicon gates, allowing both device types to coexist in the same integrated circuit without process conflicts.
2Ease of manufacture
If polysilicon strap is formed with traditional contact pad, then contact is made to polysilicon structure, but spacing between adjacent polysilicon structures cannot be reduced
Solution Approach 1:
Instead of using a traditional planar contact pad approach, the patent extends the polysilicon gate itself into the strap region, creating a three-dimensional structure that provides both the gate function and the contact function. This dimensional change eliminates the need for separate contact pads and allows reduced spacing between structures.
Solution Approach 2:
The patent merges the gate structure with the strap structure by extending the polysilicon gate into the strap region. This consolidation eliminates the need for separate contact pads and reduces the overall spacing required between adjacent polysilicon structures, thereby increasing density.
3Ease of manufacture
If poly gate is exposed with CMP process, then metal gate can be formed, but polysilicon strap is removed
Solution Approach 1:
The patent performs a preliminary etch-back of the polysilicon strap to a controlled depth before the CMP process. This preliminary action creates a topography that allows the CMP to expose the metal gate while leaving the polysilicon strap intact at lower elevations, preventing its removal during planarization.
Solution Approach 2:
The patent applies a mask to the polysilicon strap region before the CMP process to prevent its removal. This preliminary protective action counteracts the harmful effect of the CMP process on the polysilicon strap while still allowing it to expose the metal gate where needed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables low impedance contacts between polysilicon gates, enhancing memory cell density and efficiency, and allows for compact decoder designs by reducing pitch between contacts, while maintaining process compatibility with logic devices.
Implementation Method 1
The CMP exposes the sacrificial poly gate by a process called Poly Open Planarization (POP).
Implementation Method 2
a salicide process creating a polycide strap
Data Source
AI summary
A low resistance polysilicon (poly) structure includes a first poly coupled to a substrate and having a sidewall. A second poly is separated from the sidewall of the first poly and the substrate by a programming oxide. The first poly and the second poly have substantially a same planarized height above the substrate. The first poly extends from a device region to a strap region, and extends substantially parallel to a first length of the second poly. A second length of the second poly extends away from the first poly in the strap region and includes a salicide. A first diffusion region crosses the first poly and the second poly in the device region. A masked width of the first length of the second poly is defined by an etched spacer. A low resistance contact is coupled to the second length of the second poly in the strap region.