Polysilicon Semiconductor Substrate Warpage Reduction
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Solution Overview
Problem
The existing semiconductor substrates with polysilicon layers face significant stress and warpage issues due to lattice mismatch and thermal expansion differences between the polysilicon layer and the monocrystal silicon substrate, which restrict their applications and affect subsequent processing steps.
Innovation Solution
A semiconductor substrate manufacturing process involving two separate epitaxy steps for forming polysilicon layers, with controlled temperature and cooling rate adjustments to reduce stress and warpage, including isothermal annealing and oxidation treatments to manage grain boundary density and thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a polysilicon layer is formed on a monocrystal silicon substrate, then charge trapping capability is improved, but stress and warpage increase due to lattice mismatch and thermal expansion differences
Solution Approach 1:
The polysilicon layer is divided into multiple sub-layers with different thicknesses and orientations. This segmentation allows each sub-layer to have optimized grain boundary density and stress characteristics, reducing overall warpage while maintaining charge trapping capability through cumulative grain boundaries.
Solution Approach 2:
The patent systematically varies multiple parameters including polysilicon layer thickness, grain size, orientation, and density distribution. By optimizing these parameters, the patent achieves a balance where charge trapping is enhanced through increased grain boundary density while stress and warpage are controlled through appropriate thickness and material composition adjustments.
2Reliability
If the thickness of the polysilicon layer is increased, then charge capture capability is improved, but bow and warpage become more significant
Solution Approach 1:
Instead of using a single thick polysilicon layer, the patent divides it into multiple thinner sub-layers. This segmentation maintains the total thickness required for charge capture while reducing the warpage that would occur in a single thick layer, as each sub-layer has better stress distribution.
Solution Approach 2:
The patent creates a composite structure with the monocrystal silicon substrate and multi-layer polysilicon overlay. This composite approach allows optimization of each layer's properties - the substrate provides mechanical stability while the segmented polysilicon layers provide charge trapping with reduced warpage.
3Reliability
If grain boundary density is increased, then charge trapping capability is improved, but stress distribution becomes more complex
Solution Approach 1:
The patent applies different grain boundary densities to different regions and layers of the polysilicon structure. By creating local variations in grain boundary density rather than uniform distribution, the patent optimizes charge trapping in specific areas while managing stress distribution through gradient structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This process reduces stress and warpage by minimizing lattice mismatch and thermal mismatch, maintaining high grain boundary density while achieving more random grain orientation and finer grain sizes, thereby enhancing the quality and usability of the semiconductor substrate.
Implementation Method 1
Polysilicon layer has strong charge trapping capability because of its internal texture properties and high grain boundary density
Implementation Method 2
conducting an oxidation treatment to the first polysilicon layer to decrease the thickness of the first polysilicon layer
Implementation Method 3
conducting an isothermal annealing treatment to the semiconductor substrate I at the second temperature
Data Source
AI summary
The present application provides a semiconductor substrate and a preparation process thereof. In the present application, the polysilicon layer includes the first polysilicon layer and the second polysilicon layer formed separately to generate the less stress, the more random grain orientation and the smaller grain size, maintain the high grain boundary density, and enhance the charge capture. By the combination of different deposition temperature and the combination of two cooling steps after each isothermal annealing treatment, the rate of contraction between the first polysilicon layer and the second polysilicon layer and the initial semiconductor substrate is decreased, and the thermal mismatch of semiconductor substrate is reduced. The stretch between the polysilicon layer and the initial semiconductor substrate can be reduced to prevent the warpage of the semiconductor substrate. Thereby, the stress generated during the growth process of the polysilicon layer can be further reduced.