Polycrystalline Silicon Substrate via Two-Stage Metal Induced Crystallization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current methods for crystallizing amorphous silicon to polycrystalline silicon, such as MIC and MILC, result in metal catalyst residues that cause leakage current in semiconductor layers, affecting the performance of thin film transistors.
Innovation Solution
A manufacturing method involving sequential formation of an amorphous silicon layer, an insulating layer, and a metal catalyst layer, followed by two annealing steps: the first to induce crystallization and the second for lateral diffusion, allowing for removal of metal ions and reducing residues, thereby forming a polycrystalline silicon layer with minimized metal ion contamination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If MIC or MILC methods are used to crystallize amorphous silicon to polycrystalline silicon, then fine polycrystalline silicon crystals can be obtained, but metal catalyst residues remain causing leakage current in the semiconductor layer
Solution Approach 1:
The crystallization process is divided into two distinct stages: first, vertical crystallization from the substrate interface to form initial polycrystalline silicon; second, lateral crystallization along the interface to form fine-grained polycrystalline silicon. This segmentation allows metal catalysts to be concentrated at specific locations (substrate interface and lateral boundaries) that can be subsequently removed through patterning, while the bulk semiconductor layer remains free of metal residues.
Solution Approach 2:
The metal catalyst layer is completely removed after serving its crystallization function. The process extracts the harmful metal catalyst residues from the semiconductor structure by removing the entire metal catalyst layer following the two-stage crystallization process, eliminating the source of leakage current while preserving the beneficial fine crystal structure.
2Ease of manufacture
If metal catalyst layer is used to induce crystallization, then amorphous silicon can be transformed to polycrystalline silicon, but metal ions contaminate the semiconductor layer affecting transistor performance
Solution Approach 1:
The metal catalyst layer is deposited and patterned before the crystallization process begins. This preliminary action establishes controlled metal distribution that directs crystallization to occur in desired regions, with metal ions naturally concentrating at the substrate interface and lateral boundaries during the crystallization process, facilitating subsequent removal of metal-contaminated regions.
Solution Approach 2:
The metal catalyst distribution is made non-uniform through patterning, creating local concentrations at specific regions (substrate interface and lateral boundaries) rather than uniform distribution throughout the amorphous silicon layer. This local quality ensures that metal-induced crystallization occurs where needed while concentrating metal residues in removable regions, preserving transistor performance.
3Manufacturing precision
If insulating layer is placed between metal catalyst layer and amorphous silicon layer, then metal ion extension can be controlled, but additional process steps are required
Solution Approach 1:
The insulating layer serves as an intermediary between the metal catalyst layer and the amorphous silicon layer, controlling the extent and pattern of metal ion extension into the silicon during annealing. This intermediary layer enables precise spatial control of metal-induced crystallization while the metal catalyst layer itself serves multiple functions: as a catalyst source and as a pattern definition layer, reducing the need for separate patterning steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively reduces metal ion residues, decreasing leakage current and enhancing the performance of thin film transistors by concentrating metal ions at the edges of the polycrystalline silicon layer, which can be removed post-pattern, thereby improving transistor performance.
Implementation Method 1
metal ions of the metal catalyst layer extend down to the amorphous silicon layer through the insulating layer
Implementation Method 2
inducing the amorphous silicon on the amorphous silicon layer to crystallize
Implementation Method 3
metal ions lateral diffuse along the amorphous silicon layer
Implementation Method 4
inducing the amorphous silicon on the amorphous silicon layer to crystallize at the second time, forming the polycrystalline silicon layer
Implementation Method 5
anneal the substrate at the second time
Data Source
AI summary
The present invention discloses a polycrystalline silicon substrate and a manufacturing method thereof. The method comprises: provide a substrate; sequentially form an amorphous silicon layer, an insulating layer and a metal catalyst layer; anneal the substrate at the first time, so that metal ions of the metal catalyst layer extend down to the amorphous silicon layer through the insulating layer, thereby inducing the amorphous silicon on the amorphous silicon layer to crystallize at the first time; remove the insulating layer and the metal catalyst layer; anneal the substrate at the second time, so that the metal ions lateral diffuse along the amorphous silicon layer, thereby inducing the amorphous silicon on the amorphous silicon layer to crystallize at the second time, forming the polycrystalline silicon layer. Through the above way, it can reduce the metal catalyst residues during forming the polycrystalline silicon layer, decreasing the leakage current of the semiconductor layer in the thin film transistor, thereby raising the performance of the thin film transistor.