Polysilicon TFT With Asymmetric LDD Regions
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Solution Overview
Problem
Conventional polysilicon thin film transistors (TFTs) face reliability issues due to hot carrier stress and gate-induced drain leakage (GIDL), leading to decreased source/drain breakdown voltage, threshold voltage, and increased OFF current, especially as TFT size is reduced and channel length decreases.
Innovation Solution
The implementation of a polysilicon TFT substrate with a channel region and at least two lightly doped drain (LDD) regions, where the LDD regions have different impurity concentrations, is used to reduce electron mobility degradation and electric field intensity, thereby increasing ON current and decreasing OFF current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the size of conventional TFT is reduced to increase resolution, then the resolution is improved, but the channel length decreases resulting in hot carrier stress and GIDL that deteriorate reliability
Solution Approach 1:
The patent applies local quality by creating LDD regions with different impurity concentrations in specific locations between the source/drain regions and channel. The first LDD region has a first impurity concentration and the second LDD region has a second impurity concentration different from the first, allowing different parts of the same structure to have different electrical properties to manage electric field distribution locally and reduce hot carrier effects while maintaining high resolution
Solution Approach 2:
The patent changes the impurity concentration parameter by introducing two distinct LDD regions with different impurity concentrations. This parameter variation allows optimization of the electric field profile in the drain region, reducing GIDL and hot carrier stress while maintaining the shortened channel length needed for high resolution displays
2Length of moving object
If the channel length is decreased to reduce TFT size, then the device size is reduced, but electron mobility decreases due to hot carrier stress
Solution Approach 1:
The patent creates localized regions with different impurity concentrations to modify the electric field distribution specifically in areas where hot carrier effects occur. The first and second LDD regions with different impurity concentrations provide localized electric field management that protects electron mobility in the channel while maintaining the reduced channel length
Solution Approach 2:
The LDD regions act as intermediary structures between the source/drain regions and the channel. By introducing these intermediate regions with controlled impurity concentrations, the patent mediates the electric field distribution to reduce hot carrier stress on electrons traversing the channel, thereby preserving electron mobility despite the shortened channel length
3Speed
If the electric field intensity is increased to improve switching speed, then the response speed is improved, but GIDL increases due to band tunneling
Solution Approach 1:
The patent changes the impurity concentration parameter in the LDD regions to optimize the electric field profile. By carefully controlling the impurity concentrations in the first and second LDD regions, the patent achieves rapid switching speed while suppressing the peak electric field intensity that would otherwise cause excessive GIDL through band tunneling
Solution Approach 2:
The patent applies local quality by creating regions with different impurity concentrations at specific locations to manage electric field distribution. The first LDD region with its first impurity concentration and the second LDD region with its second impurity concentration create localized electric field modulation that enables fast switching while reducing GIDL in the drain region
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the reliability of TFTs by preventing electron mobility reduction and reducing the OFF current, while increasing the ON current, by effectively managing the electric field and hot carrier effects.
Implementation Method 1
a depletion region is formed in the vicinity of the drain region of the active layer due to an electric field formed between gate and drain electrodes so as to change an energy band within the LCD apparatus
Implementation Method 2
The LDD regions have an impurity concentration different from each other
Data Source
AI summary
Provided are a thin film transistor (TFT) capable of increasing ON current and decreasing OFF current values, a TFT substrate having the polysilicon TFT, a method of fabricating the polysilicon TFT, and a method of fabricating a TFT substrate having the polysilicon TFT. The polysilicon TFT substrate includes a gate line and a data line defining a pixel region, a pixel electrode formed in the pixel region, and a TFT including a gate electrode connected to the gate line, a source electrode connected to the data line, a drain electrode connected to the pixel electrode, and a polysilicon active layer forming a channel between the source and drain electrodes. The polysilicon active layer includes a channel region on which the gate electrode is superposed, source and drain regions connected to the source and drain electrode, respectively, and at least two lightly doped drain (LDD) regions y formed between the source region and the channel region and between the drain region and the channel region. The LDD regions have an impurity concentration different from each other.