Polycrystalline Silicon Thin Film Transistor Fabrication
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Solution Overview
Problem
The complexity and high cost of fabricating low-temperature polycrystalline silicon (LTPS) thin film transistor devices, which require multiple photolithography and etching processes, result in reduced yield and increased fabrication costs compared to amorphous silicon devices, while also limiting electron mobility.
Innovation Solution
A method involving the formation of a buffer layer with dopants on a substrate, followed by converting an amorphous silicon layer into a polycrystalline silicon layer through thermal processing, allowing for simultaneous dopant diffusion and threshold voltage adjustment, simplifying the process and improving electron mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If LTPS thin film transistor device is fabricated using conventional processes, then electron mobility is improved, but process complexity and fabrication cost increase
Solution Approach 1:
The patent combines multiple process steps into a unified approach. Specifically, it integrates the formation of the polycrystalline silicon layer, dopant diffusion, and threshold voltage adjustment into a single thermal processing step, eliminating the need for separate photolithography and etching processes that are traditionally required for LTPS device fabrication.
Solution Approach 2:
The thermal processing step serves multiple functions simultaneously: it converts amorphous silicon to polycrystalline silicon, diffuses dopants from the buffer layer into the active layer, and adjusts the threshold voltage. This multi-functionality reduces the overall process complexity while maintaining high electron mobility.
2Speed
If LTPS thin film transistor device is fabricated using conventional processes, then electron mobility is improved, but fabrication cost increases
Solution Approach 1:
By merging multiple process steps into a single thermal processing operation, the patent reduces the number of required equipment uses, material consumptions, and processing time, all of which contribute to lowering fabrication costs while maintaining high electron mobility.
Solution Approach 2:
The buffer layer with dopants automatically diffuses dopants into the active layer during the thermal processing step, eliminating the need for separate doping processes. This self-service mechanism reduces process complexity and fabrication cost while achieving the desired electron mobility.
3Speed
If LTPS thin film transistor device is fabricated using conventional processes, then electron mobility is improved, but yield decreases
Solution Approach 1:
The patent combines multiple critical process steps into a single thermal processing operation, reducing the number of process interfaces and potential failure points. This integration improves manufacturing yield by minimizing the cumulative effect of process variations and defects that would occur in multi-step conventional processes.
Solution Approach 2:
The in-situ dopant diffusion during thermal processing ensures uniform and controlled doping without the variability introduced by separate photolithography and etching steps. This self-regulating mechanism improves process control and increases manufacturing yield while maintaining high electron mobility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces fabrication costs, simplifies process steps, and enhances electron mobility and device characteristics by optimizing grain boundary size through thermal energy accumulation in a porous buffer layer, improving the overall performance of polycrystalline silicon thin film transistors.
Implementation Method 1
A thermal process is performed to convert the amorphous silicon layer into a polycrystalline silicon layer by means of polycrystalization
Implementation Method 2
simultaneously out-diffuse a portion of the dopants in the buffer layer into the polycrystalline silicon layer
Implementation Method 3
optimizing grain boundary size through thermal energy accumulation in a porous buffer layer
Data Source
AI summary
A method of fabricating a polycrystalline silicon thin film transistor device includes the following steps. A substrate is provided, and a buffer layer having dopants is formed on the substrate. An amorphous silicon layer is formed on the buffer layer having the dopants. A thermal process is performed to convert the amorphous silicon layer into a polycrystalline silicon layer by means of polycrystalization, and to simultaneously out-diffuse a portion of the dopants in the buffer layer into the polycrystalline silicon layer for adjusting a threshold voltage. The polycrystalline silicon layer is patterned to form an active layer. A gate insulating layer is formed on the active layer. A gate electrode is formed on the gate insulating layer. A source doped region and a drain doped region are formed in the active layer.