Polysilicon Thin Film Transistor Gate Insulator
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Solution Overview
Problem
Conventional thin film transistor (TFT) devices have unsatisfactory gate insulating layers with low dielectric strength and high leakage current due to loose texture and low formation temperature, affecting device performance and requiring extended process time.
Innovation Solution
A method for manufacturing a TFT with a dense gate insulating layer using excimer laser annealing to crystallize amorphous silicon into polysilicon, followed by thermal oxidation in an oxidizing atmosphere to form a dense thermal-oxidized gate insulating layer, which can be combined with additional layers using CVD or sputtering to enhance insulating properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional CVD or sputtering processes are used to deposit gate insulating layers, then the formation temperature can be kept low, but the resulting layer has loose texture and unsatisfactory insulating properties
Solution Approach 1:
The patent changes the deposition parameters by using plasma-enhanced CVD with specific gas compositions (silane and nitrogen in controlled ratios) and pressure conditions to deposit silicon nitride layers with superior insulating properties while maintaining low formation temperature compatible with TFT fabrication processes
Solution Approach 2:
The patent employs composite gate insulating structures combining multiple layers (such as silicon oxide and silicon nitride layers) to achieve both low formation temperature and high insulating reliability, where each layer contributes different properties to the overall gate insulating system
2Reliability
If the gate insulating layer has low dielectric strength, then manufacturing is easier, but leakage current increases and device performance deteriorates
Solution Approach 1:
The patent optimizes deposition parameters including gas flow ratios, pressure, and temperature to control the density and quality of the silicon nitride gate insulating layer, achieving high dielectric strength that suppresses leakage current while maintaining manufacturing feasibility
Solution Approach 2:
The patent uses plasma treatment and controlled oxidation processes to improve the quality and dielectric strength of the gate insulating layer, reducing leakage current through enhanced material properties rather than increasing layer thickness
3Productivity
If conventional processes are used to form gate insulating layers, then process simplicity is maintained, but process time is extended and productivity is reduced
Solution Approach 1:
The patent combines multiple functions into a single deposition process step, forming both the gate insulating layer and parts of the gate electrode structure simultaneously through plasma-enhanced CVD, thereby reducing the number of separate manufacturing steps and overall process time
Solution Approach 2:
The patent performs preliminary deposition of silicon nitride layers with optimized properties before subsequent processing steps, ensuring that the gate insulating layer is already formed with high dielectric strength and low leakage current characteristics, reducing the need for additional corrective or optimization steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method results in a dense gate insulating layer with improved electrical properties, reducing leakage current and process time, while maintaining high dielectric strength and density, suitable for various substrates and display devices.
Implementation Method 1
excimer laser annealing to crystallize amorphous silicon into polysilicon
Implementation Method 2
crystallize amorphous silicon into polysilicon
Implementation Method 3
thermal oxidation in an oxidizing atmosphere to form a dense thermal-oxidized gate insulating layer
Data Source
Figure 1~3
Figure 4~6
AI summary
Embodiments of the present invention provide a thin film transistor, a manufacturing method thereof and a display device. The method for manufacturing the thin film transistor, comprising the following steps: providing a substrate; forming a semiconductor layer on the substrate; forming a gate insulating layer; and forming a gate electrode, wherein the gate insulating layer comprises a first gate insulating layer, the first gate insulating layer being formed by oxidizing a portion of the semiconductor layer, and the unoxidized portion of the semiconductor layer forming an active layer, and wherein the gate electrode is formed in such a way that the gate insulating layer is sandwiched between the gate electrode and the active layer.