Polysilicon Thin Film Transistor Gate Insulator Stress
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current thin film transistors, particularly those using polysilicon, face challenges in maximizing carrier mobility without additional processes or structural modifications, which limits their performance in display devices.
Innovation Solution
A thin film transistor design incorporating a polysilicon active layer with a first gate insulating layer having intrinsic tensile stress in the range of 500 MPa to 800 MPa, and optionally a second gate insulating layer with intrinsic compressive stress, to alter the lattice size of polysilicon and enhance carrier mobility without additional processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If polysilicon thin film transistors are used to achieve higher carrier mobility, then display device resolution and refresh rate are improved, but the complexity of manufacturing processes increases
Solution Approach 1:
The patent applies parameter changes by introducing intrinsic stress as a new parameter to control carrier mobility. By adjusting the stress state (tensile or compressive) through gate insulating layer material selection and deposition conditions, the carrier mobility can be optimized without changing the fundamental polysilicon TFT structure or adding complex manufacturing steps. This resolves the contradiction by achieving performance improvement through parameter optimization rather than structural complexity.
2Reliability
If additional processes or structures are introduced to maximize carrier mobility, then transistor performance is improved, but manufacturing complexity and process steps increase
Solution Approach 1:
The gate insulating layer serves multiple functions: it provides electrical insulation between the gate electrode and active layer, and simultaneously introduces intrinsic stress to modulate carrier mobility. This multi-functionality eliminates the need for separate stress-inducing structures or processes, maintaining manufacturing simplicity while achieving performance optimization through the existing gate insulating layer.
3Reliability
If stress is applied to polysilicon layer to increase carrier mobility, then device performance is improved, but structural integrity may be compromised
Solution Approach 1:
The stress is applied locally and controllably through the gate insulating layer, which introduces stress only in the region beneath the gate electrode where it is most needed for carrier mobility enhancement. The stress magnitude and distribution are controlled by selecting appropriate gate insulating layer materials and deposition parameters, ensuring that structural integrity is maintained while achieving the desired electrical performance improvement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively increases carrier mobility of the thin film transistor by applying appropriate stress to the polysilicon layer, improving device performance without introducing extra processes or structures, while maintaining structural integrity.
Implementation Method 1
a first gate insulating layer having a preset intrinsic tensile stress on the active layer
Implementation Method 2
a second gate insulating layer having a preset intrinsic pressure stress on the first gate insulating layer
Data Source
AI summary
Disclosed are a thin film transistor and a manufacture method thereof. The thin film transistor according to the embodiments of the present disclosure comprises: a base substrate; an active layer composed of polysilicon on the base substrate; and a first gate insulating layer having a preset intrinsic tensile stress on the active layer.