Polycrystalline Silicon TFT Isolation Layer and Amorphous Buffer
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Solution Overview
Problem
Polycrystalline silicon thin-film transistors in LCD display panels face issues with grain size uniformity and reliability due to backlight irradiation, and the complexity of the manufacturing process requires high-precision etching, which can lead to overetching and damage to the active layer.
Innovation Solution
A polycrystalline silicon thin-film transistor structure is developed with an isolation layer whose edges are within the active layer edges, and an amorphous silicon layer is added below the isolation layer to block backlight irradiation and prevent overetching, allowing for larger grain sizes and improved uniformity, while the amorphous silicon layer can act as an active layer during etching, reducing the need for expensive etching apparatuses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a low-temperature polycrystalline silicon array substrate is used in LCD display panels, then high mobility and high response speed are achieved, but the active layer properties deteriorate due to backlight irradiation
Solution Approach 1:
An amorphous silicon layer is introduced as an intermediary between the backlight and the polycrystalline silicon active layer. This intermediate layer absorbs and blocks the backlight radiation, preventing direct irradiation of the active layer while allowing the transistor to maintain its high-speed performance characteristics
Solution Approach 2:
The amorphous silicon layer, which would normally be considered an additional process step increasing complexity, is converted into a beneficial protective element. It serves dual functions: blocking harmful backlight irradiation and potentially serving as an etching stop layer, thus transforming a potential disadvantage into a protective mechanism
2Stability of the object's composition
If excimer laser crystallization process is used to prepare active layer, then polycrystalline silicon is formed, but grain size and uniformity of crystal grains in channel region are difficult to control
Solution Approach 1:
The patent applies different treatments to different regions: the amorphous silicon layer is formed specifically in the channel region beneath the active layer, creating local structural variation that promotes uniform grain growth in the polycrystalline silicon active layer during laser crystallization, while maintaining the overall polycrystalline structure
3Manufacturing precision
If via hole etching is performed on thick intermediate insulating layer, then connection is achieved, but overetching occurs causing damage to active layer or bad contact
Solution Approach 1:
The amorphous silicon layer is deposited beforehand in the channel region, creating a cushioning or protective layer beneath the active layer. During via hole etching, this layer acts as an etching stop, preventing overetching from damaging the active layer or creating poor contacts, thus cushioning against process variations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively increases grain size and uniformity, enhances electrical properties, and improves the reliability of the device by blocking backlight irradiation and preventing overetching, thus simplifying the manufacturing process and reducing production costs.
Implementation Method 1
an amorphous silicon layer is added below the isolation layer to block backlight irradiation
Implementation Method 2
an active layer prepared by an excimer laser crystallization process
Implementation Method 3
an active layer prepared by an excimer laser crystallization process
Data Source
AI summary
A polycrystalline silicon thin-film transistor includes a substrate; an isolation layer formed on the substrate; and a polycrystalline silicon active layer formed on the substrate and the isolation layer, with two source-drain ion implantation regions being formed at both sides of the active layer, wherein the edges at both ends of the isolation layer are within the edges at both ends of the active layer. In the polycrystalline silicon thin-film transistor and the method for manufacturing the same, it is possible to increase the grain size of the active layer, improve the grain uniformity in a channel region thereof, effectively prevent deterioration of characteristics of the active layer caused by backlight irradiation, and improve the reliability of the device.