Polysilicon TFT Pixel Structure With Integrated PN Photodiode

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Solution Overview

Problem

Conventional medical amorphous silicon panel detectors have issues with thickness, optical path interference, larger occupied area, lower resolution, and higher production costs due to separate fabrication of thin film transistors and photodiodes, leading to inefficiencies in light detection.

Innovation Solution

A display panel design featuring a polysilicon thin film transistor with a PN structure formed by ion implantation, where the polysilicon layer includes doped regions to create a TFT and amorphous silicon photodiode simultaneously, reducing complexity and increasing efficiency in light detection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If separate fabrication of thin film transistor and amorphous silicon photodiode is used, then device functionality is achieved, but manufacturing complexity and production cost increase

Engineering Contradiction:
Improvemanufacturing process simplicityVSAvoidfabrication process complexity
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

The patent combines the thin film transistor and amorphous silicon photodiode into a single integrated pixel unit structure. The polysilicon layer serves dual purposes: as the transistor channel layer and as the photodiode light-sensitive layer. This merging eliminates separate fabrication processes for the two components, reducing manufacturing complexity and production cost while maintaining both transistor switching functionality and photodiode light detection capability within the same device structure

Inventive Principle:
Principle #5Merging (Combining)

2Manufacturing precision

If intermediate layer with light doping is used in amorphous silicon photodiode, then photodiode structure is formed, but panel detector thickness increases

Engineering Contradiction:
Improvephotodiode structure precisionVSAvoidpanel detector thickness
Core Design Contradiction:
Manufacturing precisionVSLength of stationary object

Solution Approach 1:

The patent merges the transistor channel layer and photodiode light-sensitive layer into a single polysilicon layer. By forming both structures simultaneously from the same layer through selective doping regions, the need for a separate intermediate layer with light doping is eliminated. This integration maintains precise photodiode structure formation while significantly reducing the overall panel detector thickness

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent changes the doping parameters within the polysilicon layer to create different functional regions. By applying different doping concentrations and types to specific regions of the polysilicon layer, the transistor channel and photodiode light-sensitive regions are differentiated without requiring additional layers. This parameter-based differentiation achieves precise structure formation while minimizing thickness

Inventive Principle:
Principle #35Parameter changes

3Length of stationary object

If thin intermediate layer is used in amorphous silicon photodiode, then panel detector thickness is reduced, but optical path interference between adjacent pixel units increases

Engineering Contradiction:
Improvepanel detector thicknessVSAvoidoptical path interference
Core Design Contradiction:
Length of stationary objectVSObject-affected harmful factors

Solution Approach 1:

The patent integrates the transistor and photodiode functions into a single polysilicon layer structure, which allows for optimized optical path design. The unified structure enables better control over light interaction, reducing stray light and optical interference between adjacent pixel units while maintaining thin profile. The integrated design allows for more efficient light collection and reduced optical path length within the active detection region

Inventive Principle:
Principle #5Merging (Combining)

4Measurement precision

If thin film transistor and amorphous silicon photodiode are disposed separately, then device functionality is achieved, but occupied area increases and resolution decreases

Engineering Contradiction:
Improvedisplay resolutionVSAvoidpixel unit occupied area
Core Design Contradiction:
Measurement precisionVSArea of stationary object

Solution Approach 1:

The patent merges the thin film transistor and amorphous silicon photodiode into a single integrated pixel unit with shared polysilicon layer. This integration eliminates the need for separate disposal of the two components, significantly reducing the occupied area per pixel unit. The compact integrated structure enables higher pixel density and improved display resolution while maintaining complete device functionality for both switching and light detection operations

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach results in a thinner, more efficient display panel with improved resolution and lower production costs by integrating the TFT and amorphous silicon photodiode fabrication, enhancing signal-to-noise ratio and reducing interference.

Implementation Method 1

a polysilicon thin film transistor with a PN structure formed by ion implantation

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Data Source

PatentUS20240096899A1Display panels
Publication Date: 2024.03.21 WUHAN CHINA STAR OPTOELECTRONICS TECH CO LTD
  • US20240096899A1 patent drawing
  • US20240096899A1 patent drawing
  • US20240096899A1 patent drawing

AI summary

Display panels are provided. The display panel includes a substrate and a thin film transistor (TFT) disposed on the substrate. The TFT includes a polysilicon layer, a gate layer, and a source-drain contacting layer. The polysilicon layer includes a first portion corresponding to the gate layer, two second portions disposed on two opposite sides of the first portion, two third portions disposed on two outer sides of the two second portions away from the first portion, and a fourth portion. The fourth portion is disposed on one of the two third portions to define a PN structure therebetween. The source-drain contacting layer is disposed on the gate layer and electrically contacts the fourth portion and the two third portions.