Polysilicon TFT Width Minimization for Off-Current Reduction
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Solution Overview
Problem
Liquid crystal display devices face challenges with off-current (leakage current) issues in thin film transistors, particularly when using polysilicon layers, which increase manufacturing complexity and costs, and existing solutions like light doped drain structures are inefficient.
Innovation Solution
A thin film transistor design featuring a polysilicon layer with an overlapping source and drain electrode configuration, where the polysilicon layer's width between the electrodes is minimized, and the amorphous silicon layer covers the polysilicon layer, reducing off-current while maintaining electron mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a polysilicon layer is used in the thin film transistor, then electron mobility is improved, but off-current increases
Solution Approach 1:
The patent applies local quality by creating different regions within the semiconductor layer: a first region with polysilicon for high electron mobility in the channel, and a second region with amorphous silicon for low off-current characteristics. This spatial differentiation of material properties allows simultaneous optimization of both electron mobility and off-current reduction in different functional areas of the transistor.
2Speed
If a top gate structure is used for p-Si TFT, then electron mobility is improved, but manufacturing complexity increases when combining with a-Si TFT
Solution Approach 1:
The patent employs a universal bottom gate structure that serves both p-Si TFT and a-Si TFT regions, eliminating the need for separate top gate structures. The gate electrode is positioned at the bottom for both transistor types, allowing a single standardized manufacturing process to produce both high-mobility p-Si TFTs and low-leakage a-Si TFTs on the same substrate without increasing device complexity.
3Object-generated harmful factors
If the polysilicon layer width is reduced, then off-current is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent utilizes parameter changes by controlling the minimum dimension of the polysilicon layer in the width direction to be smaller than the dimension of the source and drain electrodes. This dimensional parameter adjustment optimizes the balance between reducing off-current through narrower polysilicon and maintaining manufacturability, avoiding excessively tight precision requirements while achieving effective leakage reduction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces off-current while preserving electron mobility, simplifying the manufacturing process and reducing costs by minimizing the polysilicon layer's width and using a dual amorphous silicon layer to prevent electrode contact.
Implementation Method 1
an amorphous silicon layer formed so as to cover the polysilicon layer
Implementation Method 2
an n+ silicon layer formed on an upper side of the amorphous silicon layer
Data Source
AI summary
The thin film transistor includes: a gate electrode formed on a surface of a substrate; a polysilicon layer formed on an upper side of the gate electrode; an amorphous silicon layer formed on the polysilicon layer so as to cover the same; an n+ silicon layer formed on an upper side of the amorphous silicon layer; and a source electrode and a drain electrode which are formed on the n+ silicon layer, wherein, in a projected state in which the polysilicon layer, the source electrode and the drain electrode are projected onto the surface of the substrate, a part of the polysilicon layer and a part of each of the source electrode and the drain electrode are adapted so as to be overlapped with each other, and in the projected state, a minimum dimension, in a width direction orthogonal to a length direction between the source electrode and the drain electrode, of the polysilicon layer located between the source electrode and the drain electrode is smaller than dimensions in the width direction of the source electrode and the drain electrode.