Polysilicon Transistor Breakdown Voltage via LDD Structure
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Polysilicon-type liquid crystal display devices face challenges with low gate dielectric strength, making them unsuitable for high-voltage applications and limiting their performance enhancement due to issues like penetration current and short-channel effects.
Innovation Solution
The implementation of a circuit design with specific transistor configurations, including a first transistor connected to a power source and a second transistor with a bias voltage applied to its control electrode, where the bias voltage is set within a specific range relative to the power source voltages to enhance drain-source breakdown voltage and tolerance, thereby improving transistor reliability and process design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If polysilicon is used as the semiconductor layer material for thin film transistors, then the transistors can be formed using the same step as the active elements, but the gate dielectric strength becomes low and penetration current occurs, making them unsuitable for high-voltage application
Solution Approach 1:
The patent introduces an LDD (Lightly Doped Drain) structure that creates a gradient in impurity concentration within the semiconductor layer. The region adjacent to the gate electrode has lower impurity concentration than the bulk semiconductor layer, which locally enhances the gate dielectric strength and prevents penetration current while maintaining polysilicon material benefits.
Solution Approach 2:
The patent modifies the impurity concentration parameter of the semiconductor layer by forming an LDD structure with a specific impurity concentration gradient. This parameter change in the drain region allows the transistor to withstand higher voltages and prevents gate dielectric breakdown while using polysilicon material.
2Reliability
If the LDD structure is added to enhance drain-source breakdown voltage, then the BVds proof property improves, but resistance is added to the gate end portion, becoming an obstacle for higher performance
Solution Approach 1:
The LDD structure applies the impurity concentration modification only in the critical region adjacent to the gate electrode, rather than uniformly throughout the entire semiconductor layer. This localized approach enhances breakdown voltage where needed while minimizing the impact on overall transistor performance.
Solution Approach 2:
The patent uses a lightly doped (partial doping) approach in the LDD region rather than full doping. This partial action provides sufficient breakdown voltage enhancement without creating excessive resistance that would degrade transistor performance.
3Manufacturing precision
If high voltage processing is pursued for enhanced recrystallization technique, then polysilicon performance may improve, but the gate dielectric strength remains insufficient and penetration current issues persist
Solution Approach 1:
Instead of relying solely on high voltage processing to improve overall polysilicon quality, the patent applies a localized LDD structure in the drain region. This local modification specifically addresses the gate dielectric strength issue without requiring extreme high voltage processing that could damage other components.
Solution Approach 2:
The LDD structure acts as an intermediary layer between the gate electrode and the highly doped drain region. This intermediate structure with moderate impurity concentration protects the gate dielectric from direct exposure to high electric fields and heavy doping, preventing penetration current while still enabling functional operation.
Data Source
AI summary
The present invention provides a display device which can achieve the high breakdown voltage proof property, the enhancement of reliability or the expansion of the designing/process tolerance of transistors by the improvement of a circuit. A display device includes a plurality of pixels and a drive circuit which drives the plurality of pixels. The drive circuit includes a p-type first transistor which has a first electrode thereof connected to a first power source line to which a reference voltage V1 is applied, a p-type second transistor which has a first electrode thereof connected to a second electrode of the first transistor and a second electrode thereof connected to an output terminal thereof, an n-type third transistor which has a first electrode thereof connected to a second power source line to which a reference voltage V2 is applied, and an n-type fourth transistor which has a first electrode thereof connected to a second electrode of the third transistor and a second electrode thereof connected to an output terminal thereof. A first bias voltage Vcp is applied to a control electrode of the second transistor and a second bias voltage Vcn is applied to a control electrode of the fourth transistor. Further, a relationship V2<Vcp<V1 and a relationship V2<Vcn<V1 are satisfied.