Polysilicon Trench Guard Rings for LDMOSFET Latch-Up Prevention
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Solution Overview
Problem
Traditional high-voltage semiconductor devices face challenges with CMOS latch-up due to parasitic bipolar transistors, which are activated by increased parasitic resistance caused by wider spacing between transistors, leading to larger chip sizes and easier forward biasing of the base-emitter junction.
Innovation Solution
A high-voltage semiconductor device with a trench-type guard-ring structure is developed, featuring polysilicon layers and heavy doping regions within isolation trenches to absorb charge carriers and prevent PN junction formation, surrounded by insulating liners to reduce parasitic bipolar transistors and minimize chip size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the space between P-type CMOS transistor and N-type transistor is increased to prevent latch-up, then the activation of parasitic bipolar transistors is reduced, but the chip size is increased and the parasitic resistance of the base is greatly increased
Solution Approach 1:
The isolation structure is segmented into multiple functional layers: insulating liner layer, polysilicon fill layer, and conductive layer. This segmentation allows each layer to perform its specific function - the insulating liner prevents parasitic PN junction formation, the polysilicon provides charge carrier absorption, and the conductive layer ensures low resistance, collectively preventing latch-up without requiring increased transistor spacing
Solution Approach 2:
The trench isolation structure acts as an intermediary element between adjacent transistors. Instead of relying on increased spacing, the trench filled with polysilicon and covered with conductive layer serves as an active mediator that absorbs charge carriers and provides a low-resistance path, preventing parasitic bipolar transistor activation while maintaining compact layout
2Reliability
If the space between P-type CMOS transistor and N-type transistor is increased to prevent latch-up, then the activation of parasitic bipolar transistors is reduced, but the parasitic resistance of the base is greatly increased making the base-emitter junction easily forward biased
Solution Approach 1:
The conductivity of the isolation structure is changed by using heavily doped polysilicon and conductive materials in the trench isolation. This parameter change transforms the isolation structure from a high-resistance element to a low-resistance path that actively reduces parasitic base resistance, preventing forward biasing of the base-emitter junction while maintaining effective latch-up prevention
3Reliability
If additional well regions with different conductivity types are alternately arranged between transistors to prevent latch-up, then the effective base width of parasitic bipolar transistors is increased, but the chip size is increased
Solution Approach 1:
Instead of increasing the horizontal dimension (spacing or additional well regions), the solution moves to a vertical dimension approach by creating a multi-layer trench isolation structure. The trench extends vertically and is filled with functional layers that provide latch-up prevention mechanisms, allowing compact horizontal layout while achieving reliable parasitic transistor suppression
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces the number of parasitic bipolar transistors, preventing latch-up and minimizing chip size while maintaining low parasitic resistance, thus addressing the issues of CMOS latch-up and chip size expansion.
Implementation Method 1
polysilicon layers and heavy doping regions within isolation trenches to absorb charge carriers
Implementation Method 2
surrounded by insulating liners to reduce parasitic bipolar transistors and minimize chip size
Data Source
AI summary
A high-voltage semiconductor device including a semiconductor layer formed on a substrate is provided. A first well region having a first conductivity type and a second well region having a second conductivity type are formed in the semiconductor layer. Source and drain regions are respectively formed in the first and second well regions. A gate structure is disposed on the semiconductor layer. A first isolation trench structure is disposed in the semiconductor layer and surrounds the first and second well regions. The first isolation trench structure includes a first polysilicon layer filling a first trench and having the second conductivity type, a first heavy doping region formed in an upper portion of the first polysilicon layer and having the second conductivity type, and a first insulating liner disposed on sidewalls of the first trench and surrounding the first polysilicon layer.