Polysilicon Trench Fabrication for Twin Memory Cells
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Solution Overview
Problem
The existing methods for fabricating electrically programmable memory cells are complex and difficult to integrate into CMOS logic, making it challenging to produce reliable and compact non-volatile semiconductor components with efficient electrical connections between cells.
Innovation Solution
A method involving the deposition of polysilicon conducting layers, formation of trenches to create twin cells with shared electrodes, and the use of charge-trapping layers, along with silicide formation and spacer creation to simplify the fabrication process and enhance electrical connectivity between cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional fabrication methods with multiple etching and deposition steps are used, then memory cells can be formed with proper electrical isolation, but the fabrication process becomes complex and difficult to integrate into CMOS logic
Solution Approach 1:
The patent combines multiple fabrication operations into fewer steps. Specifically, the method forms trenches through the polysilicon layer and fills them with a different material (such as oxide or nitride) to create both electrical isolation and define cell regions simultaneously. This merging of isolation structure formation with cell definition eliminates the need for separate etching and deposition steps that would otherwise be required, thereby reducing fabrication complexity while maintaining proper electrical isolation between cells
Solution Approach 2:
The patent creates structures that serve multiple functions. The trenches filled with insulating material not only provide electrical isolation between adjacent memory cells but also serve as regions for forming control gates and selecting specific cells for programming or erasing operations. This multi-functionality reduces the total number of structures needed and simplifies the overall fabrication process while achieving both electrical isolation and cell selection capabilities
2Ease of manufacture
If twin cells share a common electrode structure, then fabrication steps are reduced and production costs decrease, but electrical connectivity between cells must be precisely controlled
Solution Approach 1:
The patent segments the common electrode structure into distinct regions by forming trenches that divide the shared polysilicon layer. These trenches create electrically isolated segments that can be independently controlled. The segmentation is achieved by patterning the polysilicon layer to form separate control gate regions for each cell while maintaining shared source and drain regions, thereby enabling precise electrical control over each twin cell while benefiting from shared structure fabrication
Solution Approach 2:
The patent applies different material properties to different regions of the structure. The trenches are filled with insulating material (oxide or nitride) in specific locations to create electrical isolation where needed, while leaving the polysilicon continuous in other regions to maintain electrical connectivity for shared electrodes. This local differentiation of material quality enables precise control over electrical connections between twin cells while maintaining fabrication simplicity through shared structures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the fabrication of electrically programmable memory cells, reduces production costs, and facilitates the creation of reliable and compact semiconductor components with improved electrical links between cells.
Implementation Method 1
a layer comprising a material for trapping charge is deposited on the previously formed structure
Implementation Method 2
a first conducting layer of polysilicon type is positioned on a substrate, above an insulating oxide type layer
Implementation Method 3
silicide formation and spacer creation to simplify the fabrication process and enhance electrical connectivity between cells
Data Source
AI summary
A method for fabricating at least one cell of a semiconducting component includes positioning a first conducting polysilicon-type layer on a substrate, above an insulating oxide-type layer. The production of at least one trench within the first conducting layer is included to form two electrically unlinked distinct conducting parts intended to form two transistor gates of respectively two distinct twin cells.