PON Packet Processor With Hardware Accelerators
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Solution Overview
Problem
Current packet processors for passive optical networks (PONs) face challenges in efficiently processing high-rate data streams and performing tasks such as bridge learning, ATM queuing, and packet reassembling across various PON types like GPON, BPON, and EPON with minimal latency and maximum bandwidth utilization.
Innovation Solution
A packet processor architecture comprising a core processor, hardware accelerators, and a memory unit, along with a scheduler that employs priority-based thread selection and zero-latency context switching, to efficiently handle PON traffic processing tasks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single processor is used to handle all PON traffic processing tasks, then device complexity is reduced, but processing speed and bandwidth utilization deteriorate due to the inability to handle high-rate data streams efficiently
Solution Approach 1:
The processor is segmented into a core processor and multiple specialized hardware accelerators (CRC accelerator, SHA accelerator, DES accelerator). Each accelerator handles specific processing tasks independently, allowing parallel processing of different aspects of PON traffic simultaneously, thereby increasing overall processing speed without requiring a monolithic complex processor
Solution Approach 2:
The system transitions from a single-dimensional processing model (one processor handling all tasks sequentially) to a multi-dimensional parallel processing architecture where the core processor and hardware accelerators operate simultaneously on different data streams and task types, effectively adding processing dimensions to handle high-rate data streams
2Device complexity
If software-based processing is used for all tasks, then device complexity is reduced, but processing speed deteriorates due to the overhead of software interpretation and context switching
Solution Approach 1:
The system replaces software-based processing with dedicated hardware accelerators for specific tasks such as CRC calculation, SHA hashing, and DES encryption. These hardware components perform operations at wire-speed using specialized circuitry rather than software interpretation, eliminating software overhead and context switching delays while maintaining manageable device complexity through modular architecture
Solution Approach 2:
The core processor acts as an intermediary that coordinates between the hardware accelerators and the rest of the system. It manages task distribution, collects results, and handles high-level control logic, allowing the hardware accelerators to focus on high-speed specialized operations without requiring complex inter-accelerator coordination
3Productivity
If priority-based thread selection is implemented, then processing efficiency and bandwidth utilization improve, but scheduler complexity increases
Solution Approach 1:
The scheduler uses thread priority levels as a key parameter to determine execution order and resource allocation. By changing the parameter of thread priority (assigning different priority values to different PON processing tasks), the system efficiently manages bandwidth utilization and processing efficiency without requiring complex scheduling algorithms, as the priority parameter provides a simple yet effective basis for decision-making
Data Source
AI summary
A passive optical network (PON) packet processor for processing PON traffic includes a core processor for executing threads related to the processing of PON traffic and a plurality of hardware (HW) accelerators coupled to the core processor for accelerating the processing of said PON traffic. A memory unit is coupled to the core processor for maintaining program and traffic data. In an embodiment of the present invention, the PON packet processor includes a scheduler that optimizes the execution of PON related tasks.