PON Receiver Synchronization State Machine for High-Speed Networks

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Solution Overview

Problem

High-speed passive optical networks (PON) operating at 25 Gbit/s or 50 Gbit/s face challenges with signal quality and synchronization, as existing synchronization mechanisms are not sufficiently reliable, leading to increased bit error rates and potential false synchronization or loss of sync issues.

Innovation Solution

A synchronization state machine for optical network units (ONUs) that transitions between hunt, pre-sync, sync, and re-sync states based on detection of a predefined synchronization pattern, with forward error correction (FEC) and digital equalization (DEQ) methods to ensure robust frame and symbol boundary detection, allowing for quick synchronization and loss of sync detection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If data rate is increased to 25 Gbit/s or 50 Gbit/s, then transmission speed is improved, but signal quality deteriorates and bit error rate increases

Engineering Contradiction:
Improvetransmission speedVSAvoidsignal quality
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent applies preliminary action by performing digital equalization and forward error correction decoding before final data recovery. The receiver sequentially applies DEQ to compensate for signal distortion and FEC to correct errors before determining synchronization status, allowing the system to maintain reliability at high speeds by preparing the signal in advance through multiple processing stages

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent uses an intermediary approach by introducing a multi-stage synchronization detection mechanism that operates between the raw high-speed signal and the final data output. The synchronization state machine acts as an intermediary that monitors signal quality through intermediate metrics (such as DEQ performance and FEC correction rates) and adjusts synchronization status accordingly, enabling reliable operation at 25 Gbit/s and 50 Gbit/s

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If synchronization detection is made more sensitive to detect loss of sync, then reliability is improved, but false synchronization increases

Engineering Contradiction:
Improvesynchronization detection accuracyVSAvoidfalse synchronization
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent implements feedback by continuously monitoring the outcomes of DEQ and FEC processing stages and using this information to adjust synchronization status. The synchronization state machine receives feedback from each processing stage and modifies its detection threshold dynamically, allowing it to distinguish between genuine loss of synchronization and transient signal degradation, thereby reducing false synchronization while maintaining high detection accuracy

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent applies dynamics by making the synchronization detection threshold adaptive rather than fixed. The synchronization state machine adjusts its sensitivity based on current signal conditions, becoming more stringent when false synchronization risk is high and more sensitive when signal quality is stable. This dynamic adjustment allows the system to maintain high reliability without suffering from false synchronization events

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS11750290B2Receiver synchronization for higher speed passive optical networks
Publication Date: 2023.09.05 INTEL CORP
  • US11750290B2 patent drawing
  • US11750290B2 patent drawing

AI summary

An optical network receiver (ONU) circuit associated with a passive optical network (PON) is disclosed. The ONU circuit comprises one or more processors is configured to operate in a hunt state, wherein the one or more processors is configured to detect frame boundaries associated with an incoming data signal based on a detecting a predefined synchronization (psync) pattern associated with the incoming data signal and transition to a pre-sync state, when the predefined psync pattern is detected correctly. The one or more processors is further configured to operate in the pre-sync state, wherein the one or more processors is configured to perform forward error correction (FEC) decoding for the incoming data signal, in order to determine signal statistics associated with the incoming data signal.