Semiconductor Package Ponding Recess Underfill Overflow Control

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Solution Overview

Problem

Current semiconductor packages face challenges in ensuring reliable connections and bonding strength between auxiliary chips and the package substrate, particularly due to issues with underfill layer overflow and coverage of connection pads.

Innovation Solution

The semiconductor package design incorporates a ponding recess in the solder resist layer, which allows for asymmetric placement of the underfill layer, preventing overflow and ensuring reliable electrical connections by spacing the underfill layer from lower connection pads and securely bonding the auxiliary chip to the package substrate.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Strength

If the underfill layer is applied to fill the space between the auxiliary chip and the package substrate, then the bonding strength is improved, but the underfill layer may overflow and cover the lower connection pads, causing electrical connection failures

Engineering Contradiction:
Improvebonding strengthVSAvoidelectrical connection reliability
Core Design Contradiction:
StrengthVSReliability

Solution Approach 1:

The solder resist layer is selectively removed to form a ponding recess only in the specific region where the auxiliary chip is mounted, while the solder resist layer remains intact in other regions to protect lower connection pads. This localized modification allows the underfill layer to be contained in the ponding recess without overflowing onto the connection pads, thus maintaining both bonding strength and electrical connection reliability

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The ponding recess acts as an intermediary structure between the underfill layer and the lower connection pads. By providing this intermediate containment space, the underfill layer is guided to fill only the intended gap between the auxiliary chip and package substrate, preventing direct contact with the connection pads and eliminating the harmful overflow effect

Inventive Principle:
Principle #24Intermediary (Mediator)

2Strength

If the underfill layer is applied to securely bond the auxiliary chip, then the bonding strength is improved, but it may cover and insulate the lower connection pads, preventing electrical connections

Engineering Contradiction:
Improvebonding strengthVSAvoidinsulation of connection pads
Core Design Contradiction:
StrengthVSObject-generated harmful factors

Solution Approach 1:

The solder resist layer is selectively removed to form a ponding recess only in the specific region where the auxiliary chip is mounted, while the solder resist layer remains intact in other regions to protect lower connection pads. This localized modification allows the underfill layer to be contained in the ponding recess without overflowing onto the connection pads, thus maintaining both bonding strength and electrical connection reliability

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The ponding recess acts as an intermediary structure between the underfill layer and the lower connection pads. By providing this intermediate containment space, the underfill layer is guided to fill only the intended gap between the auxiliary chip and package substrate, preventing direct contact with the connection pads and eliminating the harmful overflow effect

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20230110126A1Semiconductor packages having a package substrate and method for manufacturing the same
Publication Date: 2023.04.13 SAMSUNG ELECTRONICS CO LTD
  • US20230110126A1 patent drawing
  • US20230110126A1 patent drawing
  • US20230110126A1 patent drawing

AI summary

A semiconductor package includes a package substrate that includes a substrate base and a lower solder resist layer that covers a lower surface of the substrate base, where the lower solder resist layer includes a ponding recess that extends from a lower surface toward an upper surface of the lower solder resist layer, a semiconductor chip attached to an upper surface of the package substrate, an auxiliary chip attached to a lower surface of the package substrate adjacent to the ponding recess through a plurality of chip terminals, where the auxiliary chip includes a first side and a second side opposite to each other in a plane, and an underfill layer that fills a space between the package substrate and the auxiliary chip, surrounds the plurality of chip terminals, and fills the ponding recess.