Pooled Memory Address Translation for High-Performance Computing
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Solution Overview
Problem
As computing systems become more complex, the interconnect architecture to facilitate communication between components becomes increasingly complex to meet bandwidth requirements, while existing interconnect architectures struggle to keep pace with the growing demand for high-performance computing.
Innovation Solution
The development of a shared memory architecture that allows memory to be shared between independent nodes for exclusive or shared access using load/store (LD/ST) memory semantics, enabled by a buffered memory protocol based on a General Purpose Input/Output (GPIO) interconnect interface and protocol.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional multi-drop buses are used for interconnect, then electrical communication is achieved, but communication speed and bandwidth are insufficient for high-performance computing
Solution Approach 1:
The patent replaces traditional electrical bus-based interconnects with a packet-switched network architecture using intelligent network interfaces and protocol stacks, substituting electrical signal-based communication with data packet-based communication to achieve higher speeds and bandwidth
Solution Approach 2:
The interconnect architecture is segmented into multiple independent network interfaces, each handling specific communication tasks, allowing parallel data flows and reducing bottlenecks while maintaining manageable complexity through modular design
2Productivity
If multiple physical processors are added to increase computing power, then processing capacity improves, but communication demand between sockets increases
Solution Approach 1:
The patent introduces an intermediary packet-switched network layer between multiple physical processors, enabling efficient communication routing and data exchange that scales with the number of processors without linearly increasing communication overhead
Solution Approach 2:
The network interface architecture provides universal communication capabilities that serve multiple functions including data transfer, synchronization, and coordination across varying numbers of processors, making the system adaptable to different computing configurations
3Adaptability or versatility
If existing interconnect architectures are used, then current bandwidth requirements are met, but they cannot keep pace with growing high-performance computing demands
Solution Approach 1:
The patent implements a dynamic packet-switched network architecture where bandwidth allocation, routing paths, and communication channels can be dynamically adjusted based on workload demands, allowing the system to scale bandwidth efficiently without proportional increases in structural complexity
Solution Approach 2:
The network interface incorporates feedback mechanisms that monitor communication patterns and performance metrics, enabling adaptive routing and resource allocation that optimizes bandwidth utilization while maintaining manageable system complexity through intelligent control
Data Source
AI summary
A shared memory controller receives, from a computing node, a request associated with a memory transaction involving a particular line in a memory pool. The request includes a node address according to an address map of the computing node. An address translation structure is used to translate the first address into a corresponding second address according to a global address map for the memory pool, and the shared memory controller determines that a particular one of a plurality of shared memory controllers is associated with the second address in the global address map and causes the particular shared memory controller to handle the request.