Package-on-Package Decoupling Capacitor Layout for Low-Inductance Power
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Solution Overview
Problem
The semiconductor industry faces challenges with increased parasitic inductances due to higher switching speeds in chips, which require improved microelectronic assemblies that effectively employ decoupling capacitors to maintain constant voltage and supply sudden current demands.
Innovation Solution
A microelectronic assembly is designed with a decoupling capacitor having alternating dielectric layers and internal electrode layers, with external terminals connected to package substrates and a circuit board, to mitigate inductance issues and ensure stable power delivery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If switching speeds in chips are increased, then processing performance is improved, but parasitic inductances increase causing voltage instability
Solution Approach 1:
The patent transitions from planar capacitor layouts to three-dimensional stacked capacitor structures. Multiple capacitor layers are vertically stacked with interconnect structures connecting different layers, effectively utilizing the vertical dimension to increase capacitance density without increasing the horizontal footprint. This dimensional change allows more capacitance to be placed closer to the power delivery path, reducing parasitic inductance while maintaining voltage stability during high-speed switching.
Solution Approach 2:
The patent implements nested capacitor structures where smaller capacitors are placed within or around larger capacitor structures. Multiple capacitor elements are arranged in a nested configuration, with inner capacitors positioned within the structure of outer capacitors. This nesting approach maximizes the use of available space and creates compact power delivery networks that reduce inductance by placing capacitance closer to the load.
2Reliability
If decoupling capacitors are added to maintain constant voltage, then power delivery stability is improved, but device complexity increases
Solution Approach 1:
The patent combines multiple capacitor functions into an integrated stacked structure. Instead of placing separate discrete capacitors throughout the device, multiple decoupling capacitors are merged into a single vertical stack with shared support structures and interconnect systems. This merging reduces the number of individual components and simplifies the overall assembly process while maintaining multiple points of capacitance close to the power delivery path.
Solution Approach 2:
The stacked capacitor structure serves multiple functions simultaneously: it provides decoupling capacitance at different voltage levels, acts as an interconnect structure for power and ground signals, and functions as a space-efficient power delivery network. The same structural elements serve both mechanical support and electrical connection purposes, reducing overall device complexity while improving power delivery stability.
3Power
If more decoupling capacitors are used to supply sudden current demands, then power delivery capability is improved, but manufacturing complexity increases
Solution Approach 1:
The patent segments the capacitor structure into multiple standardized layers that can be manufactured using repeated deposition and patterning processes. Each capacitor layer follows a similar fabrication sequence, allowing for scalable manufacturing. The segmented design enables modular assembly where identical or similar capacitor units are stacked and interconnected using standardized processes, reducing manufacturing complexity despite the increased number of capacitor elements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces inductance and equivalent series resistance, enabling efficient power delivery and capacitance values, thereby addressing the challenges of maintaining constant voltage and supplying sudden current demands in high-speed semiconductor applications.
Implementation Method 1
one or more decoupling capacitors are also typically employed so that any sudden requirement for current can be supplied to the chip with the voltage maintained constant or nearly constant
Implementation Method 2
The capacitor further contains a first external terminal that is electrically connected to the first internal electrode layers and disposed on a first surface of the capacitor
Data Source
AI summary
A microelectronic assembly comprising a first package comprising a first semiconductor structure electrically connected to a first package substrate and a second package electrically connected and disposed adjacent to the first package and that comprises a second semiconductor structure electrically connected to a second package substrate is provided. The assembly also comprises a decoupling capacitor that contains alternating dielectric layers and internal electrode layers, the internal electrode layers containing first internal electrode layers and second internal electrode layers. The capacitor further contains external terminals that are disposed on a first surface of the capacitor and electrically connected to the second package substrate and external terminals disposed on the second surface of the capacitor that are electrically connected to a circuit board.