Package-on-Package Interconnects Using Conductive Studs and RDLs
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Solution Overview
Problem
Conventional package-on-package (PoP) devices face challenges in meeting fine channels and high-density routing requirements due to yield loss at ball joints, especially with the increasing size and complexity of devices driven by wide input/output memory chips, which constrain electrical performance.
Innovation Solution
The implementation of fan-out, chip-on-chip, and chip-on-substrate structures using microbumps, conductive studs, and redistribution layers (RDLs) to interconnect logic and memory chips, along with molding compounds and conductive studs extending through these layers, allows for improved interconnectivity and reduced package size, enhancing electrical performance and manufacturing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ball joint packages are used in PoP devices, then manufacturing is simpler, but yield loss occurs at the ball joint and fine channel routing requirements cannot be met
Solution Approach 1:
The patent segments the interconnection structure into multiple components: microbumps for chip-to-chip connections, conductive studs for vertical interconnections, and redistribution layers (RDLs) for routing. This segmentation allows each component to be optimized independently, eliminating the yield issues of ball joints while maintaining manufacturability through standardized processes for each segment.
Solution Approach 2:
The patent transitions from planar ball joint connections to a three-dimensional interconnection architecture using stacked microbumps, conductive studs extending through molding compound, and multiple RDL layers. This dimensional change enables fine channel routing and high-density connections without the yield penalties of conventional two-dimensional ball joints.
2Adaptability or versatility
If package size and thickness are increased to accommodate wide IO memory chips, then more routing channels are available, but electrical performance is constrained by larger dimensions
Solution Approach 1:
The patent utilizes vertical stacking of microbumps, conductive studs, and RDL layers to create high-density routing channels within a compact footprint. This three-dimensional architecture provides extensive routing capacity without increasing package lateral dimensions, thereby maintaining short signal paths and excellent electrical performance while accommodating wide IO memory chip requirements.
Solution Approach 2:
The patent implements nested interconnection structures where microbumps are positioned on chip surfaces, conductive studs extend vertically through the molding compound, and multiple RDL layers are embedded within the molding compound at different heights. This nested arrangement maximizes routing density within the available vertical space, providing high adaptability without increasing overall package thickness.
3Adaptability or versatility
If the number of package layers is increased to meet high density routing requirements, then routing capacity improves, but manufacturing complexity increases
Solution Approach 1:
The patent divides the multi-layer interconnection structure into independently manufacturable segments: microbumps formed on chip surfaces, conductive studs formed and embedded in molding compound, and RDL layers formed on separate substrates before assembly. This segmentation allows each layer to be manufactured using optimized processes, then assembled together, reducing overall manufacturing complexity while achieving high routing density.
Solution Approach 2:
The patent performs preliminary formation of microbumps on memory chips, formation of conductive studs, and creation of RDL patterns on separate substrates before final assembly. These preliminary actions allow each component to be optimized and pre-tested independently, simplifying the final assembly process and reducing manufacturing complexity despite the high number of package layers.
Data Source
AI summary
An embodiment package-on-package (PoP) device includes a package structure, a package substrate, and a plurality of connectors bonding the package structure to the package substrate. The package structure includes a logic chip bonded to a memory chip, a molding compound encircling the memory chip, and a plurality of conductive studs extending through the molding compound. The plurality of conductive studs is attached to contact pads on the logic chip.