Package-on-Package Structure With Core Material Interposer
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Solution Overview
Problem
Current package-on-package (PoP) structures face challenges in efficiently utilizing space and achieving reliable electrical connections between stacked packages, leading to limitations in density and performance, particularly in mobile devices.
Innovation Solution
The proposed solution involves forming a PoP structure where a die is disposed within a core material, with redistribution layers (RDLs) on both surfaces of the core material, allowing for efficient electrical coupling between dies and an interposer, enabling the stacking of packages without the need for additional substrates and facilitating reliable connections through conductive connectors like BGA balls.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If traditional PoP structures use separate substrates for each package, then each package can be independently manufactured and assembled, but the overall device volume and complexity increase
Solution Approach 1:
The patent merges the substrate functions by forming a single shared substrate that supports multiple packages, eliminating the need for separate substrates for each package. This consolidation reduces overall device volume and structural complexity while maintaining independent package manufacturing capabilities.
Solution Approach 2:
The shared substrate serves multiple functions simultaneously: it acts as the mounting platform for multiple packages, provides electrical interconnections between packages, and serves as the base structure for the entire PoP device. This multi-functionality reduces the number of components needed.
2Quantity of substance
If packages are stacked vertically to increase density, then space efficiency improves, but achieving reliable electrical connections between stacked packages becomes more difficult
Solution Approach 1:
The patent introduces an interposer as an intermediary component between stacked packages. The interposer provides a standardized interface with conductive vias that facilitate reliable electrical connections between packages while enabling vertical stacking. This mediator resolves the connection reliability issue by providing robust inter-package interconnects.
Solution Approach 2:
The patent transitions from planar package arrangements to vertical three-dimensional stacking. By utilizing the vertical dimension, the design achieves higher packaging density while the interposer ensures reliable electrical connections across multiple vertical layers through conductive vias and standardized interfaces.
3Reliability
If additional substrates are used to facilitate package stacking and connections, then electrical connections become more reliable, but space efficiency and density are reduced
Solution Approach 1:
The patent combines the substrate functions into a single shared substrate that supports multiple packages and provides inter-package connections. This eliminates the need for additional separate substrates, maintaining electrical connection reliability while reducing overall device volume and improving space efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances space efficiency and reliability of electrical connections, allowing for higher density packaging without the need for additional substrates, thereby improving performance in devices such as mobile phones and PDAs.
Implementation Method 1
The function chip is connected to the substrate with a plurality of solder bumps, wherein the solder bumps forming a metallurgical interconnection between the chip and the substrate.
Implementation Method 2
a plurality of conductive elements such as solder balls are arranged in a matrix array, customarily referred to as ball grid array, on a back surface of the substrate. The ball grid array allows the semiconductor package to be bonded and electrically connected to an external PCB or other electronic devices.
Implementation Method 3
The chips are connected to the substrate by a plurality of bonding gold wires.
Data Source
AI summary
A package-on-package (PoP) structure comprises a first package and a second package. The first package comprises a first die, a second die, and a core material. The core material has a first surface and a second surface. A first redistribution layer (RDL) is on the first surface, and a second RDL is on the second surface. The first die is disposed in the core material between the first surface and the second surface. The second die is coupled to one of the first RDL and the second RDL. The second package comprises a third die and an interposer. The interposer has a first side and a second side. The third die is coupled to the second side of the interposer. The first package is coupled to the second package by first electrical connectors coupled to the second side of the interposer and the first RDL.