PoP Device RDL Fan-Out Structure Thickness Reduction
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Solution Overview
Problem
Existing Package-on-Package (PoP) devices with laminate interconnection layers require the formation of through vias, which increases the vertical thickness and manufacturing complexity, limiting their suitability for compact electronic devices.
Innovation Solution
A 3D fan-out structure using a redistribution layer (RDL) instead of a laminate interconnection layer for electrical coupling between the PoP die, embedded chip, and BGA, eliminating the need for through vias and reducing the overall device thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a laminate interconnection layer with through vias is used for electrical coupling in PoP devices, then reliable electrical connection is achieved, but the vertical thickness and manufacturing complexity increase
Solution Approach 1:
The patent extracts and eliminates the through via structure from the laminate interconnection layer, replacing it with a surface-level redistribution layer (RDL) approach. This removes the need for vertical vias that increase thickness, while maintaining electrical coupling functionality through surface traces and pads on the RDL layer.
Solution Approach 2:
The patent transitions from a vertical through-via connection approach to a horizontal/surface-level RDL connection approach. By routing electrical connections along the surface of the redistribution layer rather than through vertical vias, the design achieves electrical coupling without increasing vertical thickness, effectively moving the connection path to a different dimensional plane.
2Reliability
If a laminate interconnection layer with through vias is used for electrical coupling in PoP devices, then reliable electrical connection is achieved, but manufacturing complexity increases
Solution Approach 1:
The patent removes the complex through via formation process from the manufacturing sequence. By eliminating the need to drill, fill, and planarize vertical vias through the laminate layer, the manufacturing process is simplified while maintaining electrical connection reliability through the RDL's surface-level trace and pad structure.
3Reliability
If through vias are formed in the vertical direction, then electrical coupling between PoP die, embedded chip, and BGA is achieved, but the vertical thickness increases by more than 40%
Solution Approach 1:
The patent fundamentally changes the connection geometry from vertical through-vias to horizontal surface traces on the RDL. Electrical signals are routed along the surface of the redistribution layer rather than through vertical channels, achieving the same electrical coupling function without the vertical thickness penalty of via structures.
Solution Approach 2:
Instead of routing connections vertically through the package structure via through vias, the patent inverts the approach by routing connections horizontally along the surface of the RDL. This inverted connection path achieves electrical coupling between components while minimizing vertical space consumption.
Data Source
AI summary
A method of forming a PoP device comprises placing an adhesive layer on a carrier substrate, coupling a plurality of chip packages to the adhesive layer on the carrier substrate, placing a bonding layer on the chip packages, and coupling a plurality of chips to the bonding layer on the chip packages. The method further comprises injecting a molding compound to encapsulate the chip packages and the chips on the carrier substrate, grinding the molding compound to expose a plurality of connecting elements of the chips and a plurality of second connecting elements of the chip packages, forming a redistribution layer (RDL) on the molding compound and the exposed connecting elements and second connecting elements, forming a ball grid array (BGA) on the RDL, and de-bonding the carrier substrate.