PoP Device Symmetrical Via Distribution for Bonding Integrity
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Solution Overview
Problem
The semiconductor industry faces challenges in forming package on package (PoP) devices due to issues such as poor filling of the under-fill layer, poor joints, and package shift, which affect the integration density and performance of three-dimensional integrated circuits (3DICs).
Innovation Solution
The method involves forming a PoP device using active and dummy through integrated fan-out vias or pads, where the total number and distribution of these features are symmetrical on both sides of the chip, allowing for improved bonding performance by ensuring that active elements are electrically connected and dummy elements are insulated, thereby enhancing the structural integrity and reliability of the package.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional bonding methods are used for PoP devices, then manufacturing process is simple, but bonding performance is poor with issues like poor filling of under-fill layer, poor joints, and package shift
Solution Approach 1:
The patent applies asymmetry by introducing dummy elements (dummy pads, dummy vias, dummy bumps) that are strategically placed to create symmetrical overall structure. The dummy elements compensate for the asymmetrical distribution of active elements, achieving balanced stress distribution and preventing package shift during bonding processes.
Solution Approach 2:
The patent applies local quality by differentiating between active elements (electrically connected) and dummy elements (electrically insulated). The dummy elements have the same physical structure as active elements but serve different functions - they provide mechanical support and stress distribution without electrical connectivity, improving under-fill layer filling and joint quality locally.
2Quantity of substance
If integration density is increased by reducing feature size, then more components can be integrated, but package size must be reduced which creates challenges for PoP device formation
Solution Approach 1:
The patent applies dimensionality change by transitioning from two-dimensional planar integration to three-dimensional stacked integration. Multiple chips are bonded vertically to form PoP structures, allowing high integration density without increasing the lateral package footprint. The symmetrical arrangement of active and dummy elements on each chip enables this vertical stacking approach.
3Manufacturing precision
If symmetrical distribution of active and dummy elements is implemented, then bonding performance and structural integrity are improved, but manufacturing process complexity increases
Solution Approach 1:
The patent applies merging by combining active and dummy elements into a single bonding structure that is formed and processed together. Both element types are created using the same fabrication processes (photolithography, etching, plating, bump formation), reducing the need for separate manufacturing steps and simplifying the overall process despite the increased number of elements.
Data Source
AI summary
PoP devices and methods of forming the same are disclosed. A PoP device includes a first package structure and a second package structure. The first package structure includes a first chip, and a plurality of active through integrated fan-out vias and a plurality of dummy through integrated fan-out vias aside the first chip. The second package structure includes a plurality active bumps bonded to the plurality of active through integrated fan-out vias, and a plurality of dummy bumps bonded to the plurality of dummy through integrated fan-out vias. Besides, a total number of the active through integrated fan-out vias and the dummy through integrated fan-out vias at a first side of the first chip is substantially the same as a total number of the active through integrated fan-out vias and the dummy through integrated fan-out vias at a second side of the first chip.