PoP Device With Through-Integrated Fan-Out Vias
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor industry faces challenges in achieving compact and efficient packaging of electronic components due to the limitations of existing packaging technologies, which hinder further integration density improvements and increase costs.
Innovation Solution
The method involves forming a package-on-package (PoP) device using a carrier with a de-bonding layer, a laminated film with inorganic or organic dielectric material, through-integrated fan-out vias, and a redistribution layer, allowing for the integration of multiple dies and electrical connectivity while minimizing package height through strategic film removal and underfill layer placement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional packaging technologies are used, then manufacturing simplicity is maintained, but integration density cannot be improved and costs increase
Solution Approach 1:
The patent implements package-on-package (PoP) stacking where multiple package structures are vertically integrated, with upper packages nested above lower packages. This nesting approach achieves high integration density by utilizing the vertical dimension, allowing multiple functional components to be combined in a compact footprint while maintaining manufacturing feasibility through modular assembly processes.
Solution Approach 2:
The invention transitions from planar packaging to three-dimensional vertical stacking by introducing through-integrated fan-out vias that penetrate multiple layers. This dimensional change enables electrical connectivity across stacked packages, achieving high integration density without proportionally increasing package footprint, while the standardized via structure keeps complexity manageable.
2Volume of moving object
If package height is reduced for compactness, then area is minimized, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs tunable film thickness parameters in the laminated structure to precisely control package height. By adjusting the thickness of dielectric films and conductive layers during manufacturing, the design achieves compact volume while maintaining adequate clearance for electrical isolation and mechanical integrity, balancing size reduction with manufacturing precision requirements.
Solution Approach 2:
The invention incorporates preliminary planarization and alignment steps during the lamination process to pre-establish precise geometric relationships between stacked packages. This preliminary action ensures that subsequent assembly steps can proceed with standard tolerances, reducing the cumulative precision requirements while achieving compact overall dimensions.
3Reliability
If through-integrated fan-out vias are used, then electrical connectivity is improved, but manufacturing complexity increases
Solution Approach 1:
The through-integrated fan-out vias serve multiple functions simultaneously: they provide electrical connectivity between stacked packages, enable signal redistribution across different layers, and act as mechanical anchors for the laminated structure. This multi-functionality achieves superior electrical connectivity while avoiding the need for separate via types, thereby limiting the increase in manufacturing complexity.
Solution Approach 2:
The invention merges the via formation process with the lamination and stacking processes by integrating via drilling and plating steps into the overall PoP assembly sequence. This consolidation of operations achieves reliable electrical connectivity through well-integrated via structures without requiring separate complex manufacturing lines, thereby managing overall manufacturing complexity.
Data Source
AI summary
Provided are a PoP device and a method of manufacturing the same. The PoP device includes a first package structure and a second package structure. The first package structure includes a die, a through integrated fan-out via (TIV), an encapsulant, and a film. The TIV is aside the die. The encapsulant encapsulates sidewalls of the die and sidewalls of the TIV. The film is over the TIV and the encapsulant, and aside the die. The second package structure is connected to the first package structure through a connector. The connector penetrates through the film to electrically connected to the TIV.