Package-on-Package Filling Structure for Reliable Vertical Interconnects

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Solution Overview

Problem

Current semiconductor packages face challenges in providing reliable electrical connections for stacked semiconductor packages, particularly in achieving efficient integration and miniaturization for compact and multifunctional electronic devices.

Innovation Solution

A semiconductor package design featuring a support wiring structure, a semiconductor chip, a cover wiring structure, and a filling member with connection structures that penetrate the filling member to electrically connect the support and cover wiring structures, utilizing a combination of materials like epoxy mold compounds and ceramic-based fillers to enhance reliability and reduce height.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If semiconductor packages are stacked to achieve miniaturization and multifunctionality, then integration density increases, but electrical connection reliability between stacked packages deteriorates

Engineering Contradiction:
Improveintegration densityVSAvoidelectrical connection reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The filling member is segmented into multiple layers with different material compositions. The lower filling layer contains first fillers while the upper filling layer contains second fillers with different properties, allowing each layer to optimize for specific functions such as mechanical support, electrical isolation, and stress distribution to improve connection reliability between stacked packages

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The filling member uses composite materials with different filler types in different layers. The first fillers and second fillers have different material compositions and properties, creating a composite structure that simultaneously provides mechanical support, electrical isolation, and controlled stress distribution to enhance electrical connection reliability while maintaining high integration density

Inventive Principle:
Principle #40Composite materials

2Ease of manufacture

If the filling member uses uniform material composition, then manufacturing simplicity is maintained, but electrical isolation and mechanical support performance deteriorate

Engineering Contradiction:
Improvemanufacturing simplicityVSAvoidelectrical isolation performance
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

Different regions of the filling member have different material compositions tailored to local requirements. The lower filling layer uses first fillers optimized for mechanical support and stress distribution, while the upper filling layer uses second fillers optimized for electrical isolation and planarity, allowing each region to perform its specific function effectively

Inventive Principle:
Principle #3Local quality

3Length of moving object

If connection structures are positioned close to the semiconductor chip, then electrical connection length is reduced, but risk of short circuit with the chip increases

Engineering Contradiction:
Improveconnection lengthVSAvoidshort circuit risk
Core Design Contradiction:
Length of moving objectVSObject-affected harmful factors

Solution Approach 1:

The filling member acts as an intermediary material positioned between the connection structures and the semiconductor chip. It provides electrical isolation to prevent short circuits while allowing the connection structures to maintain short connection lengths by being positioned close to the chip, thus mediating between the conflicting requirements of short connections and short circuit prevention

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS11961795B2Semiconductor package and package-on-package including the same
Publication Date: 2024.04.16 SAMSUNG ELECTRONICS CO LTD
  • US11961795B2 patent drawing
  • US11961795B2 patent drawing
  • US11961795B2 patent drawing

AI summary

A semiconductor package that includes a support wiring structure. A semiconductor chip is on the support wiring structure. A cover wiring structure is on the semiconductor chip. A plurality of connection structures penetrates a filling member and electrically connects the support wiring structure to the cover wiring structure. The filling member fills a space between the support wiring structure and the cover wiring structure. The filling member surrounds the plurality of connection structures and the semiconductor chip and includes a plurality of fillers. A partial portion of the plurality of fillers includes cutting fillers having a flat surface that extends along a vertical level that is a reference level.