Package-on-Package Thermal Management via Interposer Substrate
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Solution Overview
Problem
Package-on-package (PoP) devices face challenges in heat dissipation due to their thickness and difficulty in exhausting heat generated from semiconductor chips, which can lead to malfunction and reduced operating speed.
Innovation Solution
Incorporating an interposer substrate with high thermal conductivity, such as 10 W/mK, between the lower and upper semiconductor packages, along with thermal boundary material layers and a heat dissipating member, to facilitate effective heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If package-on-package stacking is used to achieve high performance and small size, then integration density is improved, but heat dissipation capability deteriorates
Solution Approach 1:
The patent introduces a heat dissipation member as an intermediary component positioned between the lower semiconductor chip and the interposer substrate. This heat dissipation member acts as a thermal mediator that conducts heat away from the chip, resolving the contradiction by adding a dedicated heat management component without compromising the compact PoP structure.
Solution Approach 2:
The patent employs composite material structures including thermal boundary material layers with specific thermal conductivity properties positioned between the semiconductor chip and interposer substrate. These composite material arrangements optimize heat transfer while maintaining the structural integrity and electrical functionality of the PoP device.
2Adaptability or versatility
If package thickness is increased to accommodate multiple semiconductor chips, then functionality is improved, but heat exhaustion capability deteriorates
Solution Approach 1:
The patent addresses heat dissipation in the vertical dimension by introducing thermal boundary material layers and heat dissipation members that operate along the thickness direction of the PoP device. This dimensional approach to heat management allows multiple functional layers to coexist while maintaining effective heat exhaustion pathways through the stacked structure.
3Temperature
If thermal boundary material layers with high thermal conductivity are used, then heat dissipation is improved, but manufacturing complexity increases
Solution Approach 1:
The patent specifies thermal boundary material layers with particular thermal conductivity parameters (e.g., greater than 10 W/mK) to optimize heat dissipation. By defining specific parameter ranges for thermal properties, the patent achieves effective heat management while providing clear manufacturing specifications that balance performance requirements with manufacturing feasibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances heat exhaustion from the lower semiconductor chip, improving the operating speed of the PoP device and reducing malfunctions by rapidly dissipating heat, thereby delaying dynamic thermal management and minimizing CPU frequency loss.
Implementation Method 1
an interposer substrate disposed between the lower semiconductor package and the upper semiconductor package... the interposer substrate may have a thermal conductivity of about 10 watts per meter Kelvin (W/mK) or more
Implementation Method 2
a first thermal boundary material layer disposed between the lower semiconductor package and the interposer substrate
Implementation Method 3
a heat dissipating member disposed within the substrate body... the heat dissipating member may include at least one of a metal or graphite
Data Source
AI summary
The inventive concepts provide package-on-package (PoP) devices. In the PoP devices, an interposer substrate and a thermal boundary material layer may be disposed between a lower semiconductor package and an upper semiconductor package to rapidly exhaust heat generated from a lower semiconductor chip included in the lower semiconductor package. The interposer substrate may be formed of one or more insulating layers, conductive vias, heat dissipating members, protection layers, and various conductive patterns.