PoP Semiconductor Package Molding With Laser-Textured Cooling Surface
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge of effectively dissipating heat in semiconductor packages with stacked semiconductor devices, particularly in Package on Package (PoP) structures, where increased complexity hinders efficient heat dissipation as the number of chips increases.
Innovation Solution
A semiconductor package design featuring a molding with a marking pattern and an uneven structure, including trenches and column structures, formed using laser beams to enhance heat dissipation by increasing the surface area in contact with air.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If multiple semiconductor packages are stacked in PoP structure, then device size is reduced and performance is increased, but heat dissipation becomes more difficult
Solution Approach 1:
The patent introduces vertical column structures protruding from the molding surface, transforming a flat 2D surface into a 3D structure with increased surface area. This dimensional change allows heat to dissipate from multiple levels, effectively addressing the heat dissipation challenge in stacked PoP devices while maintaining compact footprint.
Solution Approach 2:
The molding structure incorporates trenches and column structures that create a porous-like geometry with increased surface area-to-volume ratio. This porous configuration enhances heat exchange with the surrounding environment, improving thermal management without increasing the overall device volume.
2Productivity
If the number of semiconductor chips in the stack increases, then performance is increased, but heat generated inside the package increases
Solution Approach 1:
By adding vertical column structures that protrude from the molding surface, the patent creates additional heat dissipation pathways in the vertical dimension. This allows heat from multiple stacked chips to be dissipated through elevated surfaces, preventing heat accumulation as chip count increases.
Solution Approach 2:
The molding is segmented into multiple regions with trenches and column structures, dividing the heat dissipation function across multiple discrete elements. This segmentation increases the total surface area available for heat dissipation, enabling effective thermal management in high-performance multi-chip stacks.
3Adaptability or versatility
If the structure of the semiconductor package becomes more complicated, then device functionality is enhanced, but it is more difficult to dissipate heat
Solution Approach 1:
The patent applies local quality by creating uneven structures with column structures and trenches in specific regions of the molding. These localized structural variations provide enhanced heat dissipation at critical areas without requiring complete structural complexity throughout the entire package, thus managing heat effectively while maintaining functional versatility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design efficiently dissipates heat generated within the semiconductor package by maximizing the contact area with air, thereby improving thermal management and reducing the complexity of heat dissipation in stacked semiconductor devices.
Implementation Method 1
A marking pattern is formed by a first laser beam on a first region of an upper surface of the molding
Implementation Method 2
An uneven structure is formed by a second laser beam on a second region of the upper surface of the molding
Data Source
AI summary
A semiconductor package includes a first package substrate. A first semiconductor device is mounted on an upper surface of the first package substrate. A first molding is disposed on the first package substrate and covers the first semiconductor device. A second package substrate is disposed on the first molding. At least one second semiconductor device is mounted on an upper surface of the second package substrate. A second molding covers the second semiconductor device. The second molding has a marking pattern in the first region. The second molding has an uneven structure having a plurality of trenches that define a plurality of column structures protruding from a second region on the second semiconductor device.