POP Semiconductor Package Interface for Adhesion Reliability
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Solution Overview
Problem
The package-on-package (POP) technique in semiconductor packaging often experiences adhesion failure between upper and lower packages, leading to reliability issues.
Innovation Solution
A semiconductor package design that includes a lower substrate with a chip mounting region, an interconnection region, and an outer region, featuring multiple solder resist patterns and a vertical connection structure to enhance electrical connectivity and prevent adhesion failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a package-on-package (POP) structure is used to achieve miniaturization and high performance, then the integration density is improved, but adhesion failure occurs between upper and lower packages
Solution Approach 1:
A third solder resist pattern is introduced as an intermediary element between the upper substrate and lower substrate. This intermediate layer directly contacts the upper substrate and provides a bonding interface that prevents adhesion failure, while allowing the POP structure to maintain its high integration density.
Solution Approach 2:
The patent uses a composite structure combining multiple solder resist patterns (first, second, and third patterns) with different functions. The third solder resist pattern forms a composite bonding interface with the upper substrate, creating a multi-layer composite structure that enhances adhesion reliability while maintaining the compact POP architecture.
2Reliability
If multiple solder resist patterns are added to prevent adhesion failure, then adhesion reliability is improved, but device complexity increases
Solution Approach 1:
The third solder resist pattern serves multiple functions simultaneously: it provides adhesion between the upper and lower substrates, acts as an insulating layer, and forms part of the bonding interface. This multi-functionality reduces the need for additional separate components, thereby limiting the increase in device complexity while improving adhesion reliability.
3Reliability
If the third solder resist pattern directly contacts the upper substrate, then adhesion reliability is improved, but manufacturing precision requirements increase
Solution Approach 1:
The third solder resist pattern is formed and positioned in advance during the manufacturing process, creating a pre-established bonding interface. This preliminary action allows for controlled alignment and reduces the precision requirements during subsequent assembly steps, as the bonding interface is already prepared and positioned correctly.
Data Source
AI summary
A semiconductor package includes a lower substrate having a chip mounting region, an interconnection region surrounding the chip mounting region, and an outer region surrounding the interconnection region, and includes a lower wiring layer. A first solder resist pattern has first openings exposing bonding regions of the lower wiring layer. A semiconductor chip is on the chip mounting region and is electrically connected to the lower wiring layer. A second solder resist pattern is on the first solder resist pattern on the interconnection and outer regions and is spaced apart from the semiconductor chip, and includes second openings disposed on the first openings. An upper substrate covers the semiconductor chip, and includes an upper wiring layer. A vertical connection structure is on the interconnection region and electrically connects the upper and lower wiring layers. A solder resist spacer is on the second solder resist pattern on the outer region.