POP Semiconductor Package Layout for Bonding Height and Warpage
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving both increased integration and reliability, particularly in stacked structures like POP, where warpage and bonding height issues affect structural integrity.
Innovation Solution
A semiconductor package design featuring a lower substrate with embedded passive elements and connection structures, supported by support members on the semiconductor chip's side surfaces and substrate edges, along with an upper substrate overlapping in a vertical direction, allowing for multiple semiconductor chips to be stacked with enhanced electrical connections and encapsulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple semiconductor chips are stacked in a POP structure to increase integration, then the functionality and density are improved, but warpage and bonding height issues occur that deteriorate structural reliability
Solution Approach 1:
The support structures are segmented into multiple discrete support members distributed around the perimeter of the lower substrate, rather than using a single continuous support structure. This segmentation allows for localized reinforcement at critical areas while maintaining flexibility elsewhere, effectively managing warpage in the stacked POP structure without compromising overall structural reliability
Solution Approach 2:
The support members are combined with the connection structures (such as bumps or pads) to form an integrated reinforcement system. This merging of support functions with existing connection elements provides both mechanical support and electrical connection, addressing structural reliability issues while maintaining the high integration density of the stacked chips
2Reliability
If support structures are added to reduce warpage and secure bonding height, then structural reliability is improved, but device complexity increases
Solution Approach 1:
The support members are designed to serve multiple functions: providing mechanical support to prevent warpage, maintaining bonding height for reliable connections, and potentially serving as electrical connection points. This multi-functionality reduces the need for separate dedicated support structures, thereby limiting the increase in device complexity while achieving improved bonding height stability
Data Source
AI summary
A semiconductor package includes a lower substrate comprising a lower interconnection layer. A first semiconductor chip is on the lower substrate and electrically connected to the lower interconnection layer. Connection structures are on the lower substrate and surround the first semiconductor chip. Support members are disposed on at least a portion of connection structures adjacent to side surfaces of the first semiconductor chip and edges of the lower substrate. An upper substrate is on the first semiconductor chip and the connection structures, and comprises an upper interconnection layer. A second semiconductor chip is on the upper substrate and is electrically connected to the upper interconnection layer. A third semiconductor chip is on the upper substrate and is electrically connected to the upper interconnection layer, spaced apart from the second semiconductor chip in a horizontal direction, and overlaps the first semiconductor chip in a vertical direction.