Semiconductor package and manufacturing method thereof
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing package-on-package (PoP) type semiconductor packages face challenges in achieving improved structural reliability, reduced thickness, and weight, while also requiring efficient manufacturing processes that minimize time and cost.
Innovation Solution
A semiconductor package design featuring a package substrate, semiconductor chip, adhesive layer that softens but does not melt, conductive pillars, and an interposer structure, which enhances adhesion and connectivity between components, thereby improving structural reliability and reducing thickness and weight.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional PoP semiconductor package structure is used, then multiple semiconductor chips can be integrated, but the structural reliability is insufficient
Solution Approach 1:
The package structure is segmented into distinct functional layers: adhesive layer, molding layer, and conductive pillars. Each layer performs a specific function (adhesion, protection, electrical connection) which collectively improves structural reliability without requiring complex integrated solutions
Solution Approach 2:
The patent employs composite material structures combining adhesive layers with molding layers and conductive pillars. This composite approach creates a multi-functional structure that enhances reliability by distributing mechanical and electrical stresses across different material properties
2Weight of stationary object
If the thickness of semiconductor packages is decreased to reduce weight, then portability is improved, but structural reliability deteriorates
Solution Approach 1:
The adhesive layer is applied locally at critical interfaces (between semiconductor chip and substrate, and between interposer and substrate) rather than uniformly throughout the package. This localized reinforcement provides structural reliability at key stress points while maintaining overall package thinness and weight reduction
3Productivity
If manufacturing processes are simplified to reduce time and cost, then productivity is improved, but manufacturing precision may deteriorate
Solution Approach 1:
The adhesive layer is pre-applied to the substrate before mounting the semiconductor chip and interposer. This preliminary action ensures proper positioning and adhesion from the start, maintaining manufacturing precision while simplifying the overall process by eliminating the need for post-assembly adhesive application or complex alignment procedures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves enhanced structural reliability, reduced thickness, and weight, while also reducing the manufacturing time and cost are reduced.
Implementation Method 1
the adhesive layer may include a material that becomes soft but does not completely dissolve or melt when heat is applied thereto
Data Source
AI summary
A semiconductor package includes: a package substrate; a semiconductor chip mounted above the package substrate; a chip connection terminal arranged between the semiconductor chip and the package substrate; an adhesive layer arranged on the package substrate to cover a side and a top surface of the semiconductor chip and surrounding the chip connection terminal between the semiconductor chip and the package substrate; a molding layer arranged on the package substrate and surrounding the adhesive layer; an interposer including an interposer substrate mounted on the adhesive layer and the molding layer; and a conductive pillar arranged on the package substrate to surround the side of the semiconductor substrate and configured to penetrate the molding layer in a vertical direction and connect the package substrate to the interposer substrate.